LFE3-35EA-8LFTN256I Lattice, LFE3-35EA-8LFTN256I Datasheet - Page 101
LFE3-35EA-8LFTN256I
Manufacturer Part Number
LFE3-35EA-8LFTN256I
Description
FPGA - Field Programmable Gate Array 33.3K LUTs 133 I/O 1.2V -8 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-35EA-8LFTN256I
Rohs
yes
Factory Pack Quantity
90
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-8LFTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Timing Characteristics
AC and DC Characteristics
Table 3-17. Transmit
Table 3-18. Receive and Jitter Tolerance
T
Z
J
J
1. Rise and fall times measured with board trace, connector and approximately 2.5pf load.
2. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter.
3. Jitter values are measured with each CML output AC coupled into a 50-ohm impedance (100-ohm differential impedance).
4. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.
5. Values are measured at 1.25 Gbps.
RL
RL
Z
J
J
J
J
T
1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. The sinusoidal jitter tolerance mask is shown in Figure 3-18.
2. Jitter values are measured with each high-speed input AC coupled into a 50-ohm impedance.
3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.
4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled.
5. Values are measured at 1.25 Gbps.
TX_DDJ
TX_TJ
RX_DJ
RX_RJ
RX_SJ
RX_TJ
RF
TX_DIFF_DC
RX_DIFF
RX_EYE
Symbol
RX_DIFF
RX_CM
2, 3, 4, 5
1, 2, 3, 4, 5
1, 2, 3, 4, 5
1, 2, 3, 4, 5
1, 2, 3, 4, 5
Symbol
3, 4, 5
Differential return loss
Common mode return loss
Differential termination resistance
Deterministic jitter tolerance (peak-to-peak)
Random jitter tolerance (peak-to-peak)
Sinusoidal jitter tolerance (peak-to-peak)
Total jitter tolerance (peak-to-peak)
Receiver eye opening
Differential rise/fall time
Differential impedance
Output data deterministic jitter
Total output data jitter
Description
Description
3-48
From 100 MHz to 1.25 GHz
From 100 MHz to 1.25 GHz
Test Conditions
Test Conditions
20%-80%
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
Min.
80
—
—
—
Min.
0.29
80
10
—
—
—
—
6
Typ.
100
80
—
—
Typ.
100
—
—
—
—
—
—
—
Max.
0.10
0.24
120
—
Max.
0.34
0.26
0.11
0.71
120
—
—
—
Ohms
Units
ps
UI
UI
Ohms
Units
dB
dB
UI
UI
UI
UI
UI
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