LFE3-150EA-8LFN1156I Lattice, LFE3-150EA-8LFN1156I Datasheet - Page 75

• Manufacturer Part Number: LFE3-150EA-8LFN1156I
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -8 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-8LFN1156I

• Rohs: yes
• Factory Pack Quantity: 24

LatticeECP3 External Switching Characteristics (Continued)
Generic DDRX2 Output with Clock and Data (>10 Bits Wide) Centered at Pin Using PLL (GDDRX2_TX.PLL.Centered)
Left and Right Sides
t
t
f
Memory Interface
DDR/DDR2 I/O Pin Parameters (Input Data are Strobe Edge Aligned, Output Strobe Edge is Data Centered)
t
t
t
t
f
f
DDR3 (Using PLL for SCLK) I/O Pin Parameters
t
t
t
t
f
DDR3 Clock Timing
t
t
t
t
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond or ispLEVER soft-
2. General I/O timing numbers based on LVCMOS 2.5, 12mA, Fast Slew Rate, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O.
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18.
5. DDR3 timing numbers based on SSTL15.
6. Uses LVDS I/O standard.
7. The current version of software does not support per bank skew numbers; this will be supported in a future release.
8. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
9. Using settings generated by IPexpress.
10. These numbers are generated using best case PLL located in the center of the device.
11. Uses SSTL25 Class II Differential I/O Standard.
12. All numbers are generated with ispLEVER 8.1 software.
DVBGDDR
DVAGDDR
MAX_GDDR
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR
MAX_DDR2
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR3
CH
CL
JIT
JIT
(avg)
(per, lck)
(cc, lck)
(avg)
ware.
Parameter
9
9
9
9
Data Valid Before CLK
Data Valid After CLK
DDRX2 Clock Frequency
Data Valid After DQS (DDR Read) All ECP3 Devices
Data Hold After DQS (DDR Read) All ECP3 Devices
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
DDR2 clock frequency
Data Valid After DQS (DDR Read) All ECP3 Devices
Data Hold After DQS (DDR Read) All ECP3 Devices
Data Valid Before DQS
Data Valid After DQS
DDR3 clock frequency
Average High Pulse Width
Average Low Pulse Width
Output Clock Period Jitter During
DLL Locking Period
Output Cycle-to-Cycle Period Jit-
ter During DLL Locking Period
Description
Over Recommended Commercial Operating Conditions
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
Device
3-22
Min. Max. Min. Max. Min. Max. Min. Max.
0.64
0.25
0.25
0.64
0.25
0.25
0.47
0.47
285
285
125
300
-90
—
—
95
—
—
-9
0.225
0.225
0.53
0.53
500
200
266
400
180
DC and Switching Characteristics
—
—
—
—
—
—
—
—
90
LatticeECP3 Family Data Sheet
0.64
0.25
0.25
0.64
0.25
0.25
0.47
0.47
285
285
125
300
-90
95
—
—
—
—
-8
0.225
0.225
0.53
0.53
500
200
266
400
180
90
—
—
—
—
—
—
—
—
0.64
0.25
0.25
0.64
0.25
0.25
0.47
0.47
370
370
125
266
-90
95
—
—
—
—
1, 2
-7
4
0.225
0.225
0.53
0.53
420
200
200
333
180
90
—
—
—
—
—
—
—
—
10
0.64
0.25
0.25
0.64
0.25
0.25
0.47
0.47
431
432
125
266
-90
95
—
—
—
—
-6
0.225
0.225
0.53
0.53
375
166
166
300
180
90
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
ps
ps
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
ps
ps