PCI-MT64-O4-N1 Lattice, PCI-MT64-O4-N1 Datasheet - Page 115
PCI-MT64-O4-N1
Manufacturer Part Number
PCI-MT64-O4-N1
Description
FPGA - Field Programmable Gate Array PCI Master/Target 64B
Manufacturer
Lattice
Datasheet
1.PCI-MT32-O4-N2.pdf
(193 pages)
Specifications of PCI-MT64-O4-N1
Factory Pack Quantity
1
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Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-44. 32-bit Target Burst Write Transaction With a 64-bit Local Interface (Continued)
Dual Address Cycle (DAC)
The PCI master uses a Dual Address Cycle (DAC) to inform the PCI IP core, operating as a target, that it is using
64-bit addressing with two back-to-back address phases. The PCI IP core can respond to 64-bit addressing when
the memory address being accessed is over the 4GB limit. 64-bit addressing is not restricted to only 64-bit configu-
rations of the PCI IP core.
Figure 2-40
description of the dual address cycle.
CLK
10
8
9
shows an example of the DAC during a 32-bit read transaction.
Turn around
PCI Data
Cleanup
Phase
Idle
Quad Word Aligned
The Core puts Data 3 on lt_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master relinquishes control of
framen, ad and cben. It also de-asserts irdyn if both trdyn and irdyn were asserted last
cycle.
The Core de-asserts lt_hdata_xfern. If both irdyn and trdyn are asserted on the previous
cycle, the Core asserts lt_ldata_xfern to the back-end to signify Data 3 was transferred suc-
cessfully. With lt_ldata_xfern asserted, the back-end doesn’t write the data yet nor increment
the address counter. It de-asserts both devseln and trdyn if both trdyn and irdyn were
asserted last cycle.
The Core de-asserts lt_ldata_xfern. If lt_rdyn is asserted on the previous cycle, the Core
asserts lt_hdata_xfern to signify to the back-end that it can safely write the QWORD (Data 3
and Don’t care).
The Core signals to the back-end that the transaction is complete by clearing bar_hit. It also de-
asserts lt_hdata_xfern.The target relinquishes control of devseln and trdyn.
115
Description
Table 2-45
Functional Description
PCI IP Core User’s Guide
gives a clock-by-clock
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