iCE40LP1K-CM121 Lattice, iCE40LP1K-CM121 Datasheet - Page 4

• Manufacturer Part Number: iCE40LP1K-CM121
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM121

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 95
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-121
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 490

April 2013
Architecture Overview
The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Non-
volatile Programmable Configuration Memory (NVCM) and blocks of sysMEM™ Embedded Block RAM (EBR) sur-
rounded by Programmable I/O (PIO). Figure 2-1 shows the block diagram of the iCE40-1K device.
Figure 2-1. iCE40-1K Device, Top View
The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional
grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the
periphery of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register
functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of
interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The
place and route software tool automatically allocates these routing resources.
In the iCE40 family, there are up to four independent sysIO banks. Note on some packages V
together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this
document. The sysMEM EBRs are large 4 Kbit, dedicated fast memory blocks. These blocks can be configured as
RAM, ROM or FIFO.
The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have mul-
tiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the
clocks.
Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40
includes on-chip, Nonvolatile Configuration Memory (NVCM).
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Configuration Memory
Non-volatile
NVCM
(NVCM)
Programmable Interconnect
I/O Bank 2
I/O Bank 0
iCE40 LP/HX Family Data Sheet
PLL
Phase-Locked
Loop
2-1
4-Input Look-up
Bank
SPI
Table (LUT4)
Carry Logic
Flip-flop with Enable
and Reset Controls
Logic Block (PLB)
Programmable
Architecture
DS1040
CCIO
Data Sheet DS1040
Architecture_01.1
banks are tied