iCE40LP1K-CM36 Lattice, iCE40LP1K-CM36 Datasheet - Page 11
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iCE40LP1K-CM36
Manufacturer Part Number
iCE40LP1K-CM36
Description
FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
Manufacturer
Lattice
Datasheet
1.ICE40LP8K-CM121.pdf
(42 pages)
Specifications of iCE40LP1K-CM36
Rohs
yes
Number Of Gates
1280
Number Of Logic Blocks
16
Number Of I/os
25
Maximum Operating Frequency
533 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
CBGA-36
Distributed Ram
64 Kbit
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
490
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICE40LP1K-CM36
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
iCE40LP1K-CM36TR
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
Figure 2-6. iCE I/O Register Block Diagram
Table 2-6. PIO Signal List
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of
standards that are found in today’s systems including LVCMOS and LVDS25.
Each bank is capable of supporting multiple I/O standards including single-ended LVCMOS buffers and differential
LVDS25E output buffers. Bank 3 additionally supports differential LVDS25 input buffers. Each sysIO bank has its
own dedicated power supply.
OUTPUT_CLK
CLOCK_ENABLE
INPUT_CLK
OUTPUT_ENABLE
D_OUT_0/1
D_IN_0/1
LATCH_INPUT_VALUE
Pin Name
LATCH_INPUT_VALUE
LATCH_INPUT_VALUE
OUTPUT_ENABLE
OUTPUT_ENABLE
CLOCK_ENABLE
OUTPUT_CLK
INPUT_CLK
D_OUT_1
D_OUT_0
D_OUT_1
D_OUT_0
D_IN_1
D_IN_0
D_IN_1
D_IN_0
= Statically defined by configuration program.
I/O Type
Output
Input
Input
Input
Input
Input
Input
2-8
Output register clock
Clock enable
Input register clock
Output enable
Data to the core
Data from the core
Latches/holds the Input Value
(1,0)
(1,0)
0
1
0
1
(1,0)
(1,0)
iCE40 LP/HX Family Data Sheet
Description
PIO Pair
Pad
Pad
Architecture