LFE3-95EA-9FN672I Lattice, LFE3-95EA-9FN672I Datasheet - Page 31
LFE3-95EA-9FN672I
Manufacturer Part Number
LFE3-95EA-9FN672I
Description
FPGA - Field Programmable Gate Array 92K LUTs 295 I/O 1.2V -9 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-95EA-9FN672I
Rohs
yes
Number Of Gates
92 K
Number Of Logic Blocks
240
Embedded Block Ram - Ebr
4420 Kbit
Number Of I/os
295
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-672
Distributed Ram
188 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
230.7 mA
Factory Pack Quantity
40
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-95EA-9FN672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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MULTADDSUBSUM DSP Element
In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands BA and BB of Slice 0. Additionally, the operands AA and AB are multiplied and the
result is added/subtracted with the result of the multiplier operation of operands BA and BB of Slice 1. The results
of both addition/subtractions are added by the second ALU following the slice cascade path. The user can enable
the input, output and pipeline registers. Figure 2-30 and Figure 2-31 show the MULTADDSUBSUM sysDSP ele-
ment.
Figure 2-30. MULTADDSUBSUM Slice 0
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
I
C
IR
AA
MULTA
OR
PR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-28
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
OR
PR
LatticeECP3 Family Data Sheet
IR
BB
IR
COUT
SROB
SROA
DSP Slice
Next
Architecture
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