LFE3-150EA-9FN672C Lattice, LFE3-150EA-9FN672C Datasheet - Page 69

• Manufacturer Part Number: LFE3-150EA-9FN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -9 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-9FN672C

• Rohs: yes
• Number Of Gates: 149 K
• Number Of Logic Blocks: 372
• Embedded Block Ram - Ebr: 6850 Kbit
• Number Of I/os: 380
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-672
• Distributed Ram: 303 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 370.9 mA
• Factory Pack Quantity: 40

LatticeECP3 External Switching Characteristics
Clocks
Primary Clock
f
t
t
t
f
t
t
t
f
t
t
t
f
t
t
t
Edge Clock
f
t
t
f
t
t
f
t
t
f
t
t
Generic SDR
General I/O Pin Parameters Using Dedicated Clock Input Primary Clock Without PLL
t
t
t
t
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_PRI
W_PRI
SKEW_PRI
SKEW_PRIB
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
MAX_EDGE
W_EDGE
SKEW_EDGE_DQS
CO
SU
H
SU_DEL
Parameter
6
6
Frequency for Primary Clock Tree
Clock Pulse Width for Primary
Clock
Primary Clock Skew Within a
Device
Primary Clock Skew Within a Bank ECP3-150EA
Frequency for Primary Clock Tree
Pulse Width for Primary Clock
Primary Clock Skew Within a
Device
Primary Clock Skew Within a Bank ECP3-70EA/95EA
Frequency for Primary Clock Tree
Pulse Width for Primary Clock
Primary Clock Skew Within a
Device
Primary Clock Skew Within a Bank ECP3-35EA
Frequency for Primary Clock Tree
Pulse Width for Primary Clock
Primary Clock Skew Within a
Device
Primary Clock Skew Within a Bank ECP3-17EA
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge
of the Device
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge
of the Device
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge
of the Device
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge
of the Device
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Description
Over Recommended Commercial Operating Conditions
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
Device
3-16
Min. Max. Min. Max. Min. Max. Min. Max.
0. 8
0. 9
0. 9
0.8
0.8
0.9
0.0
1.5
1.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-9
500
300
250
500
360
310
500
300
250
500
200
500
200
500
200
DC and Switching Characteristics
3.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1, 2
2
LatticeECP3 Family Data Sheet
0. 8
0. 8
0. 9
0. 9
0. 9
0.8
0.8
0.9
0.0
1.5
1.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-8
500
300
250
500
360
310
500
300
250
500
310
220
500
200
500
200
500
200
500
200
3.9
—
—
—
—
—
—
—
—
—
—
—
0.9
0.9
0.9
0.9
1.0
1.0
1.0
1.0
0.0
1.7
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
420
330
280
420
370
320
420
330
280
420
340
230
420
210
420
210
420
210
420
210
4.3
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
1.0
1.0
1.2
1.2
1.2
1.2
0.0
2.0
1.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
375
360
300
375
380
330
375
360
300
375
370
240
375
220
375
220
375
220
375
220
4.7
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ps
ps
ns
ps
ps
ns
ps
ps
ns
ps
ps
ns
ps
ns
ps
ns
ps
ns
ps
ns
ns
ns
ns