M24C64-DFMN6TP STMicroelectronics, M24C64-DFMN6TP Datasheet - Page 41
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M24C64-DFMN6TP
Manufacturer Part Number
M24C64-DFMN6TP
Description
EEPROM 64 Kbit Serial I2C 1.7V to 5.5V EEPROM
Manufacturer
STMicroelectronics
Datasheet
1.M24C64-WBN6.pdf
(42 pages)
Specifications of M24C64-DFMN6TP
Product Category
EEPROM
Rohs
yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
M24C64-W M24C64-R M24C64-F M24C64-DF
Table 25.
16-Dec-2011
28-Aug-2012
Date
Document revision history (continued)
Revision
26
27
Updated A dimension in
scale package mechanical
Datasheet split into:
– M24C64-DF, M24C64-W, M24C64-R,M24C64-F (this datasheet) for
tandard products (range 6),
– M24C64-125 datasheet for automotive products (range 3).
Added 8-bump thin WLCSP.
Updated single supply voltage and number of Write cycles on cover
page.
Updated
(SDA).
Updated
Added
Section 5.1: Write operations
updated.
Moved
enabled)
Section 5.1.2: Page
Figure
Case of locked Write identification Page removed from
Lock Identification Page (M24C64-D
Updated
and move
Section 5.1.6: Minimizing Write delays by polling on
Added note 1 in
Table 7: Operating conditions (voltage range
Added
updated
Removed note 2 in
t
Table 24: Ordering information
temperature for device grade 5 and added Note
packages.
WLDL,
Doc ID 16891 Rev 27
t
9.
Section 4.5: Device
Table 11: Cycling performance by groups of four bytes
DHWH, and
Figure 8: Write mode sequences with WC = 0 (data write
Table 12: Memory cell data
Section 2.1: Serial Clock (SCL)
Figure 6: Block
Section 5.1.5: ECC (Error Correction Code) and Write cycling
to
Figure 10: Write cycle polling flowchart using ACK
Section 5.1.1: Byte
Table 6: Operating conditions (voltage range W)
t
NS.
Table 16: 400 kHz AC characteristics
Write: changed address bits to A15/A5 and updated
Table 22: WLCSP-R 5-bump wafer-length chip-
diagram.
data.
addressing.
move to
scheme: removed ambient operating
Changes
Write.
retention.
only).
Section 5: Instructions
and
R).
Section 2.2: Serial Data
2.
to MLP8 and WLCSP
ACK.
Revision history
Section 5.1.4:
for t
QL1QL2,
and
to
and
and
41/42