CAV25160VE-GT3 ON Semiconductor, CAV25160VE-GT3 Datasheet - Page 7

• Manufacturer Part Number: CAV25160VE-GT3
• Description: EEPROM 16KB SPI SER CMOS EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAV25160VE-GT3

• Product Category: EEPROM

Byte Write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 10 significant address
bits are used by the CAV25080 and 11 by the CAV25160.
The rest are don’t care bits, as shown in Table 11. Internal
programming will start after the low to high CS transition.
During an internal write cycle, all commands, except for
RDSR (Read Status Register) will be ignored. The RDY bit
will indicate if the internal write cycle is in progress (RDY
high), or the device is ready to accept commands (RDY
low).
Table 11. BYTE ADDRESS
CAV25080
CAV25160
Once the WEL bit is set, the user may execute a write
SCK
SCK
SO
CS
SO
CS
SI
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
Device
0
0
0
0
0
0
1
1
0
0
2
HIGH IMPEDANCE
2
0
0
3
3
OPCODE
OPCODE
0
0
4
4
Address Significant Bits
0
0
5
5
1
1
6
A10 − A0
6
A9 − A0
0
0
Figure 6. Page WRITE Timing
Figure 5. Byte WRITE Timing
7
7
A
A
N
N
8
8
BYTE ADDRESS*
BYTE ADDRESS*
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HIGH IMPEDANCE
21 22 23 24 25 26 27
21 22 23 24−31 32−39
7
Page Write
host may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following
CAV25080/160 is automatically returned to the write
disable state.
Address Don’t Care Bits
A
A
After sending the first data byte to the CAV25080/160, the
0
0
Byte 1
D7 D6 D5 D4 D3 D2 D1 D0
Data
A15 − A10
A15 − A11
* Please check the Byte Address Table (Table 11)
* Please check the Byte Address Table (Table 11)
Byte 2
Data
DATA IN
completion
Byte 3
DATA IN
Data
24+(N−1)x8−1 .. 24+(N−1)x8
28
Data Byte N
of
7..1
29 30 31
the
# Address Clock Pulse
0
write
24+Nx8−1
16
16
cycle,
the