MAX5802AAUB+T Maxim Integrated, MAX5802AAUB+T Datasheet - Page 18

• Manufacturer Part Number: MAX5802AAUB+T
• Description: Digital to Analog Converters - DAC 12-Bit 2Ch DAC w/I2C
• Manufacturer: Maxim Integrated

Specifications of MAX5802AAUB+T

• Rohs: yes

In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5800/MAX5801/MAX5802. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5800/MAX5801/
MAX5802, followed by a STOP condition.
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitch-
ing or digital feedthrough to the DACs while the interface
is active.
A master device communicates with the MAX5800/
MAX5801/MAX5802 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed by an
acknowledge clock (ACK) pulse as shown in the
and
MAX5800/MAX5801/MAX5802 with R/W = 0 to indicate
a write. The second byte contains the register (or com-
Figure 5. Multiple Register Write Sequence (Standard I
Maxim Integrated
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
Figure
SDA
SCL
START
5. The first byte contains the address of the
I
2
C Command Byte and Data Bytes
DACs with Internal Reference and I
BYTE #1: I
0 0 0 1 1 A1 A0
WRITE ADDRESS
2
C SLAVE ADDRESS
I
2
C Write Operations
A
ACK. GENERATED BY MAX5800/MAX5801/MAX5802
W
A
23
23
BYTE #2: COMMAND1 BYTE
BYTE #5: COMMANDn BYTE
22
22
WRITE COMMAND1
21
21
(B[23:16])
(B[23:16])
20 19 18 17
20 19 18 17
Figure 4
2
C Protocol)
MAX5800/MAX5801/MAX5802
16
16
A
A
15 14 13 12 11 10 9
15 14 13 12 11 10 9
BYTE #3: DATA1 HIGH BYTE
BYTE #6: DATAn HIGH BYTE
DATA PAIRS (3 BYTE BLOCKS)
ADDITIONAL COMMAND AND
mand) to be written and the third and fourth bytes contain
the data to be written. By repeating the register address
plus data pairs (Byte #2 through Byte #4 in
and
writes using a single I
no limit as to how many registers the user can write with
a single command. The MAX5800/MAX5801/MAX5802
support this capability for all user-accessible write mode
commands.
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in
the address of the MAX5800/MAX5801/MAX5802 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5800/
MAX5801/MAX5802 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are pro-
vided, the MAX5800/MAX5801/MAX5802 will continue to
readback ones.
Readback of individual CODE registers is supported for
the CODE command (B[23:20] = 0000). For this com-
mand, which supports a DAC address, the requested
Combined Format I
WRITE DATA1
Figure
(B[15:8])
(B[15:8])
5), the user can perform multiple register
8
8
A
A
7 6 5 4 3 2 1
BYTE #4: DATA1 LOW BYTE
7 6 5 4 3 2 1
BYTE #7: DATAn LOW BYTE
2
C command sequence. There is
WRITE DATA1
Figure
2
(B[7:0])
(B[7:0])
C Readback Operations
2
6. The first byte contains
C Interface
0
0
A
A
COMMAND1
EXECUTED
COMMANDn
EXECUTED
STOP
Figure 4
18