MAX5590AEUG+ Maxim Integrated, MAX5590AEUG+ Datasheet - Page 25

• Manufacturer Part Number: MAX5590AEUG+
• Description: Digital to Analog Converters - DAC 256-Tap Digi Pot
• Manufacturer: Maxim Integrated

Specifications of MAX5590AEUG+

• Rohs: yes
• Number Of Converters: 8
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Minimum Operating Temperature: - 40 C
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V

Settling-Time-Mode Write Example:
To configure DACA and DACD into FAST mode and
DACB and DACC into SLOW mode, use the command
in Table 13.
To read back the settling-time-mode bits, use the com-
mand in Table 14.
The
MAX5590–MAX5595 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the DAC’s
CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or
CPOL = 1 and CPHA = 1 for MICROWIRE and SPI
applications requiring the clocking of data in on the ris-
Table 13. Settling-Time-Mode Write Example
X = Don’t care.
Table 14. Settling-Time-Mode Read Command
X = Don’t care.
Table 15. CPOL and CPHA Bits
Table 16. CPOL and CPHA Write Command
X = Don’t care.
Table 17. CPOL and CPHA Read Command
X = Don’t care.
D OU TRB
D OU TRB
DATA
DATA
DIN
DATA
DIN
DATA
DIN
DIN
CPOL
0
0
1
1
CPOL
1
1
X
1
X
1
CONTROL BITS
CONTROL BITS
CONTROL BITS
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
and
CPHA
1
0
X
0
X
1
0
1
0
1
______________________________________________________________________________________
CPHA
0
1
CPOL and CPHA Control Bits
X
0
1
X
Default values at power-up when DSP is connected to DV
of SCLK.
Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge
of SCLK.
Data is clocked in on the falling edge of SCLK.
Data is clocked in on the rising edge of SCLK.
CONTROL BITS
0
1
control
X
X
1
0
1
0
1
X
0
X
bits
0
0
X
0
X
0
of
0
0
X
0
X
0
the
0
0
X
X
1
1
ing edge of SCLK. Set the DAC’s CPOL and CPHA bits
to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =
0 for DSP and SPI applications, requiring the clocking
of data in on the falling edge of SCLK (refer to the
Programmer’s Handbook and see Table 15 for details).
At power-up, if DSP = DV
is zero and if DSP = DGND, the default value of CPHA
is one. The default value of CPOL is zero at power-up.
To write to the CPOL and CPHA bits, use the command
in Table 16.
To read back the device’s CPOL and CPHA bits, use
the command in Table 17.
S P D H S P D G S P D F S P D E S P D D S P D C S P D B S P D A
X
X
DESCRIPTION
Voltage-Output DACs
X
X
X
DATA BITS
DATA BITS
DATA BITS
X
X
X
X
X
DD
X
X
X
X
X
. Data is clocked in on the rising edge
DATA BITS
X
X
X
X
X
DD
, the default value of CPHA
X
1
X
X
X
X
0
X
X
X
C P O L C P H A
C P O L C P H A
X
X
0
X
X
1
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