74LVC4245AD NXP Semiconductors, 74LVC4245AD Datasheet

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74LVC4245AD

Manufacturer Part Number
74LVC4245AD
Description
Bus Transceivers XCVR 8BIT LVL SHIFTR
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC4245AD

Product Category
Bus Transceivers
Rohs
yes
Logic Type
CMOS
Logic Family
74LVC
Number Of Channels Per Chip
8
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
10 ns
Supply Voltage - Max
3.6 V, 5.5 V
Supply Voltage - Min
1.5 V
Maximum Operating Temperature
+ 125 C
Package / Case
SO-24
Function
Bus Transceiver with Voltage Translation
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Circuits
1
Polarity
Non-Inverting
Factory Pack Quantity
30
Part # Aliases
74LVC4245AD,112

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1. General description
2. Features and benefits
The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. It is designed to
interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.
The device features an output enable input (pin OE) for easy cascading and a
send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the
buses are effectively isolated.
In suspend mode, when V
other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be
smaller than V
V
CC(A)
74LVC4245A
Octal dual supply translating transceiver; 3-state
Rev. 10 — 18 December 2012
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Wide supply voltage range:
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
Complies with JEDEC standard no. JESD8B/JESD36
ESD protection:
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
 V
3 V bus (V
5 V bus (V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC(B)
diode
, except in suspend mode.
CC(B)
CC(A)
(typical 0.7 V).
): 1.5 V to 3.6 V
): 1.5 V to 5.5 V
CC(A)
CC(A)
is zero, there will be no current flow from one supply to the
= 0 V
Product data sheet

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74LVC4245AD Summary of contents

Page 1

Octal dual supply translating transceiver; 3-state Rev. 10 — 18 December 2012 1. General description The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions designed ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74LVC4245AD 40 C to +125 C 74LVC4245ADB 40 C to +125 C 74LVC4245APW 40 C to +125 C 74LVC4245ABQ 4. Functional diagram 22 G3 3EN1 2 3EN2 mna452 Fig 1 ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVC4245A V 1 CC(A) DIR GND 11 GND 12 001aaa349 Fig 3. Pin configuration SO24 and (T)SSOP24 5.2 Pin description Table 2. Pin description Symbol V CC(A) V CC(B) GND DIR A[0:7] B[0:7] OE 74LVC4245A Product data sheet Octal dual supply translating transceiver; 3-state ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Functional table Input OE DIR [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply current CC C input capacitance I C input/output capacitance I/O = 40 C to +125 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage V ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply current CC [1] All typical values are measured at V [2] For transceivers, the parameter 3.6 V: other inputs at V CC( 4 5.5 V: other inputs at V CC(A) 10 ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). V Symbol Parameter Conditions t output skew sk(o) time C power 5 V bus An; PD dissipation V = GND capacitance V CC(A outputs enabled outputs disabled 3 V bus Bn GND CC(B outputs enabled outputs disabled ...

Page 9

... NXP Semiconductors = 1 2.7 V  CC( 0 CC(A) CC(A) V and V are typical output voltage drops that occur with the output load Fig 6. Input (An, Bn) to output (Bn, An) propagation delays OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH = 1 2.7 V  V ...

Page 10

... NXP Semiconductors Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 8. Load circuitry for switching times Table 8. Test data Supply voltage V V CC(A) CC(B) < 2.7 V < 3 ...

Page 11

... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 10 ...

Page 13

... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors 13. Abbreviations Table 9. Abbreviations Acronym Description ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 10. Revision history Document ID Release date 74LVC4245A v.10 20121218 • Modifications: V CC(A 74LVC4245A v.9 20121120 • Modifications: Figure 74LVC4245A v.8 20111122 74LVC4245A v.7 20110812 74LVC4245A v.6 20080118 74LVC4245A v ...

Page 16

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... Octal dual supply translating transceiver; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 18

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations ...

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