74LVC544ADB NXP Semiconductors, 74LVC544ADB Datasheet

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74LVC544ADB

Manufacturer Part Number
74LVC544ADB
Description
Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC544ADB

Product Category
Bus Transceivers
Rohs
yes
Logic Type
CMOS
Logic Family
LVC
Number Of Channels Per Chip
8
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
17 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.2 V
Maximum Operating Temperature
+ 125 C
Package / Case
SSOP-24
Function
Latched Transceiver
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Circuits
1
Polarity
Inverting
Factory Pack Quantity
59
Part # Aliases
74LVC544ADB,112
1. General description
2. Features and benefits
The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type
latches for temporary storage of the data flow in either direction. Separate latch enable
inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for
each register to permit independent control of input and output in either direction of the
data flow.
The 74LVC544A contains eight D-type latches, with separate inputs and controls for each
set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be
LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With
pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B
latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data
into the latches where it is stored and the B outputs no longer change with the A inputs.
With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display
the data present at the outputs of the A latches.
74LVC544A
Octal D-type registered transceiver; inverting; 3-state
Rev. 4 — 18 December 2012
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Supports partial power-down applications; inputs/outputs are high-impedance when
V
Complies with JEDEC standard:
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C
CC
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
= 0 V
Product data sheet

Related parts for 74LVC544ADB

74LVC544ADB Summary of contents

Page 1

Octal D-type registered transceiver; inverting; 3-state Rev. 4 — 18 December 2012 1. General description The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type latches for temporary storage of the data flow in either direction. ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC544AD 40 C to +125 C 74LVC544ADB 40 C to +125 C 74LVC544APW 4. Functional diagram OEBA 13 OEAB 11 EAB ...

Page 3

... NXP Semiconductors OEBA EBA LEBA OEAB EAB LEAB An Fig 3. Logic diagram 5. Pinning information 5.1 Pinning Fig 4. Pin configuration for SO24 and (T)SSOP24 74LVC544A Product data sheet Octal D-type registered transceiver; inverting; 3-state identical channels To 7 other channels 1 LEBA OEBA ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin LEBA 1 OEBA EAB 11 GND 12 OEAB 13 LEAB EBA 74LVC544A Product data sheet Octal D-type registered transceiver; inverting; 3-state ...

Page 5

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Disabled Disabled plus latch Latch plus display Transparent Hold (do nothing) [ for direction and BA for direction H = HIGH voltage level L = LOW voltage level h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB and EBA l = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB and EBA X = don’ ...

Page 6

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output GND; O current I power-off OFF CC leakage current I supply current I additional per input pin; ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t enable time OEBA to An; OEAB to Bn; see EBA to An; EAB to Bn; see ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t output skew 3.6 V sk(o) CC time C power V = GND dissipation capacitance [1] Typical values are measured at T [2] ...

Page 10

... NXP Semiconductors LEXX input An, Bn output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 6. Latch enable input (LEXX) pulse width and latch enable input to output (An, Bn) propagation delays An, Bn input ...

Page 11

... NXP Semiconductors OEXX, EXX input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 8. 3-state enable and disable times Table 8. Measurement points ...

Page 12

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 9. Load circuitry for switching times Table 9 ...

Page 13

... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 11 ...

Page 15

... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 16

... Revision history Document ID Release date 74LVC544A v.4 20121218 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74LVC544A v.3 20040511 74LVC544A v.2 19980729 74LVC544A v ...

Page 17

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 18

... Octal D-type registered transceiver; inverting; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 19

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations ...

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