74LVCH245AD-T NXP Semiconductors, 74LVCH245AD-T Datasheet
74LVCH245AD-T
Specifications of 74LVCH245AD-T
Related parts for 74LVCH245AD-T
74LVCH245AD-T Summary of contents
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... Octal bus transceiver; 3-state Rev. 7 — 5 April 2012 1. General description The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. ...
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... Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC245AD 74LVCH245AD 40 C to +125 C 74LVC245ADB 74LVCH245ADB 40 C to +125 C 74LVC245APW 74LVCH245APW 40 C to +125 C 74LVC245ABQ 74LVCH245ABQ 40 C to +125 C 74LVC245ABX 74LVCH245ABX 4. Functional diagram ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVC245A 74LVCH245A DIR GND 10 001aak292 Fig 3. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin DIR GND ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function selection Inputs OE DIR [ HIGH voltage level LOW voltage level don’t care high impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output current GND 3 power-off 5 OFF I O leakage V current I supply GND current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation nAn to nBn; nBn to nAn; see pd delay enable time nOE to nAn, nBn; see ...
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... NXP Semiconductors 11. AC waveforms See Table 8 for measurement points V and V are typical output voltage levels that occur with the output load Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF ...
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... NXP Semiconductors negative positive Test data is given in Table 9. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 7. Test circuit for measuring switching times Table 9 ...
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... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 0.019 inches 0.1 0.01 0.004 0.089 0.014 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 9 ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0.30 4 0.2 0.00 0.18 4.4 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.30 4.6 3.35 mm 0.5 0.00 0.18 3.05 4.4 OUTLINE ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status 74LVC_LVCH245A v ...
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... NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations ...