74LVC543ABQ-G NXP Semiconductors, 74LVC543ABQ-G Datasheet
74LVC543ABQ-G
Specifications of 74LVC543ABQ-G
Related parts for 74LVC543ABQ-G
74LVC543ABQ-G Summary of contents
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Octal D-type registered transceiver; 3-state Rev. 8 — 18 December 2012 1. General description The 74LVC543A is an octal registered transceiver containing two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC543AD 40 C to +125 C 74LVC543ADB 74LVC543APW 40 C to +125 C 74LVC543ABQ 40 C to +125 C 4. Functional diagram ...
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... NXP Semiconductors Fig 3. Logic diagram 74LVC543A_8 Product data sheet OEBA EBA LEBA OEAB EAB LEAB IDENTICAL CHANNELS to 7 other channels All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 December 2012 74LVC543A Octal D-type registered transceiver; 3-state mna750 © ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVC543A LEBA 1 OEBA EAB 11 GND 12 001aaa341 Fig 4. Pin configuration for SO24 and (T)SSOP24 5.2 Pin description Table 2. Pin description Symbol Pin LEBA 1 LEAB 14 OEBA 2 OEAB 13 EBA 23 EAB 11 A[0: ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Functional table Operating modes Input OEAB, OEBA Disabled H X Disabled plus latch L L Latch plus display L L Transparent L L Hold (do nothing HIGH voltage level L = LOW voltage level HIGH must be present one set-up time before the LOW to HIGH transition of LEAB, LEBA, EAB and EBA LOW must be present one set-up time before the LOW to HIGH transition of LEAB, LEBA, EAB and EBA X = don’ ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output current GND power-off OFF CC leakage current I supply current I additional per input pin; ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t enable time OEBA to An; OEAB to Bn; see EBA to An; EAB to Bn; see ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t hold time An LEAB, LEBA, EAB, EBA; h see Figure output skew 3.6 V sk(o) ...
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... NXP Semiconductors LEAB, LEBA input An, Bn output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 7. Latch enable input (LEAB, LEBA) pulse width and latch enable input to output An and Bn propagation delays ...
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... NXP Semiconductors An, Bn input LEAB, LEBA EAB, EBA input Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times for the inputs An and Bn to LEAB, LEBA and EAB, EBA inputs Table 8 ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 10. Test circuit for measuring switching times Table 9 ...
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... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 12 ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Changed interlacing into interfacing (errata) in features list. 74LVC543A v.7 20121129 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74LVC543A v.6 20040407 74LVC543A v ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations ...