MK20DX64VLF5 Freescale Semiconductor, MK20DX64VLF5 Datasheet - Page 27

• Manufacturer Part Number: MK20DX64VLF5
• Description: ARM Microcontrollers - MCU Kinetis 64K Flex
• Manufacturer: Freescale Semiconductor

Specifications of MK20DX64VLF5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K20P32M50SF0
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Freescale Semiconductor, Inc.
Symbol
Symbol
I
J
t
DDOSC
pll_lock
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
each PCB and results will vary.
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
D
acc_pll
D
V
lock
DD
unl
dco_t
) over voltage and temperature should be considered.
PLL accumulated jitter over 1µs (RMS)
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Supply voltage
Supply current — low-power mode (HGO=0)
Description
Description
• f
• f
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
vco
vco
= 48 MHz
= 100 MHz
Table 14. Oscillator DC electrical specifications
Table 13. MCG specifications (continued)
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Table continues on the next page...
± 1.49
± 4.47
1.71
Min.
Min.
—
—
—
—
—
—
—
—
—
Peripheral operating requirements and behaviors
1350
Typ.
Typ.
600
500
200
300
950
1.2
1.5
—
—
—
—
150 × 10
+ 1075(1/
± 2.98
± 5.97
f
Max.
pll_ref
Max.
3.6
—
—
—
—
—
—
—
—
)
-6
Unit
Unit
mA
mA
μA
μA
μA
nA
ps
ps
%
%
V
s
Notes
Notes
8
9
1
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