W65C816S6PLG-14 Western Design Center (WDC), W65C816S6PLG-14 Datasheet - Page 8

• Manufacturer Part Number: W65C816S6PLG-14
• Description: Microprocessors - MPU 8/16-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C816S6PLG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit, 16 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 27

2 W65C816S FUNCTIONAL DESCRIPTION
The W65C816S provides the design engineer with upward software compatibility from 8-bit W65C02S in
applications to 16-bit system application. In Emulation mode, the W65C816S offers many advantages,
including full software compatibility with W65C02S coding.
Internal organization of the W65C816S can be divided into two parts: 1) The Register Section and 2) The
Control Section. Instructions obtained from program memory are executed by implementing a series of data
transfers within the Register Section. Signals that cause data transfers to be executed are generated within
the Control Section. The W65C816S has a 16-bit internal bus architecture with an 8-bit external data bus
and 24-bit external address bus.
2.1
An Operation Code enters the processor on the Data Bus, and is latched into the IR during the opcode fetch
cycle. This opcode is then decoded, along with timing and interrupt signals, to generate various IR control
signals for use during instruction operations.
2.2
The Timing Control Unit keeps track of each instruction cycle as it is executed. The TCU is set to zero each
time an instruction fetch is executed, and is advanced at the beginning of each cycle for as many cycles as
is required to complete the instruction. Each data transfer between registers depends upon decoding the
contents of both the Instruction Register and the Timing Control Unit.
2.3
All Arithmetic and Logic Unit operations take place within the 16-bit ALU. In addition to data operations, the
ALU also calculates the effective address for relative and indexed addressing modes. The result of a data
operation is stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags may
be updated following the ALU data operation.
2.4
The Accumulator is a general purpose register which contains one of the operands and the result of most
arithmetic and logical operations. In the Native mode (E=0), when the Accumulator Select Bit (M) equals
zero, the Accumulator is established as 16 bits wide (A, B=C). When the Accumulator Select Bit (M) equals
one, the Accumulator is 8 bits wide (A). In this case, the upper 8 bits (B) may be used for temporary storage
in conjunction with the Exchange Accumulator (XBA) instruction.
2.5
During modes of operation, the 8-bit Data Bank Register holds the bank address for memory transfers. The
24-bit address is composed of the 16-bit instruction effective address and the 8-bit Data Bank address. The
register value is multiplexed with the data value and is present on the Data/Address lines during the first half
of a data transfer memory cycle for the W65C816S. The DBR is initialized to zero during Reset.
Instruction Register (IR)
Timing Control Unit (TCU)
Arithmetic and Logic Unit (ALU)
Accumulator (A)
Data Bank Register (DBR)
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