EFM32GG332F1024 Energy Micro, EFM32GG332F1024 Datasheet - Page 7

• Manufacturer Part Number: EFM32GG332F1024
• Description: ARM Microcontrollers - MCU 1024KB FL 128KB RAM
• Manufacturer: Energy Micro

Specifications of EFM32GG332F1024

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: Giant Gecko (GG)
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 1024 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.85 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• Interface Type: I2C, SPI, USB, UART
• Number Of Programmable I/os: 50
• Program Memory Type: Flash

2.1.27 Advanced Encryption Standard Accelerator (AES)
2.1.28 General Purpose Input/Output (GPIO)
2.2 Configuration Summary
2012-09-11 - EFM32GG332FXX - d0126_Rev1.00
power domain enables the EFM32GG332 to keep track of time and retain data, even if the main power
source should drain out.
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
In the EFM32GG332, there are 50 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advances configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
The features of the EFM32GG332 is a subset of the feature set described in the EFM32GG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M3
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
USB
I2C0
I2C1
USART0
USART1
USART2
LEUART0
Preliminary
Configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
IrDA
I2S
I2S
Full configuration
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7
Pin Connections
NA
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
NA
NA
NA
NA
CMU_OUT0, CMU_OUT1
NA
NA
USB_VBUS, USB_VBUSEN,
USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
I2C0_SDA, I2C0_SCL
I2C1_SDA, I2C1_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
US2_TX, US2_RX, US2_CLK, US2_CS
LEU0_TX, LEU0_RX
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