MAX1177BEUP-T Maxim Integrated, MAX1177BEUP-T Datasheet - Page 7

• Manufacturer Part Number: MAX1177BEUP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1177BEUP-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 135 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 91 dB
• Interface Type: Parallel
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1177 uses a successive-approximation (SAR)
conversion technique with an inherent track-and-hold
(T/H) stage to convert an analog input into a 16-bit digital
output. Parallel outputs provide a high-speed interface to
microprocessors (µPs). The Functional Diagram shows a
simplified internal architecture of the MAX1177. Figure 3
shows a typical operating circuit for the MAX1177.
Figure 1. Load Circuits
Figure 2. MAX1177 Timing Diagram
DO–D15
1mA
D7/D15–D0/D8
a) HIGH-Z TO V
DGND
V
V
OL
OH
TO V
TO HIGH-Z
HBEN
EOC
R/C
_______________________________________________________________________________________
CS
OH
, AND
OH
C
,
Detailed Description
LOAD
= 20pF
t
t
HIGH-Z
CSL
DH
Converter Operation
16-Bit, 135ksps, Single-Supply ADC
b) HIGH-Z TO V
DO–D15
V
V
t
OH
OL
ACQ
TO HIGH-Z
TO V
1mA
t
CSH
OL
DV
, AND
OL
DD
,
t
DOWN CONTROL
DS
C
DGND
REF POWER-
LOAD
= 20pF
with 0 to 10V Input Range
t
CONV
The MAX1177 has an input scaler, which allows conver-
sion of input voltages ranging from 0 to 10V, while oper-
ating from a single +5V analog supply. The input scaler
attenuates and shifts the analog input to match the input
range of the internal digital-to-analog converter (DAC).
Figure 4 shows the equivalent input circuit of the
MAX1177. This circuit limits the current going into AIN to
less than 2mA.
In track mode, the internal hold capacitor acquires the
analog signal (Figure 4). In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
During the acquisition, the analog input (AIN) charges
capacitor C
falling edge of CS. At this instant, the T/H switches
open. The retained charge on C
ple of the input. In hold mode, the capacitive DAC
adjusts during the remainder of the conversion time to
restore node T/H OUT to zero within the limits of 16-bit
resolution. Force CS low to put valid data on the bus
after conversion is complete.
t
DV
t
t
DO
DO
HOLD
BYTE VALID
HIGH/LOW
. The acquisition ends on the second
t
DO1
BYTE VALID
HIGH/LOW
HOLD
t
t
EOC
BR
Track and Hold (T/H)
represents a sam-
Analog Input
HIGH-Z
Input Scaler
7