EFM32LG332F256 Energy Micro, EFM32LG332F256 Datasheet - Page 4

• Manufacturer Part Number: EFM32LG332F256
• Description: ARM Microcontrollers - MCU 256KB FL 32KB RAM
• Manufacturer: Energy Micro
• Series: EFM32LG332r

Specifications of EFM32LG332F256

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: EFM32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.85 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-64
• Mounting Style: SMD/SMT
• Interface Type: I2C, I2S, SPI, UART, USART
• Length: 10 mm

2.1.4 Direct Memory Access Controller (DMA)
2.1.5 Reset Management Unit (RMU)
2.1.6 Energy Management Unit (EMU)
2.1.7 Clock Management Unit (CMU)
2.1.8 Watchdog (WDOG)
2.1.9 Peripheral Reflex System (PRS)
2.1.10 Universal Serial Bus Controller (USB)
2.1.11 Inter-Integrated Circuit Interface (I2C)
2012-09-11 - EFM32LG332FXX - d0111_Rev1.00
into two blocks; the main block and the information block. Program code is normally written to the main
block. Additionally, the information block is available for special user data and flash lock bits. There is
also a read-only page in the information block containing system and device calibration data. Read and
write operations are supported in the energy modes EM0 and EM1.
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
The RMU is responsible for handling the reset functionality of the EFM32LG.
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32LG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board
the EFM32LG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device,
On-the-go (OTG) Dual Role Device or Host-only configuration. In OTG mode the USB supports both
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both full-
speed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal dedicated
Descriptor-Based Scatter/Garther DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in
addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for
supplying 5V to VBUS when operating as host.
The I
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
2
C module provides an interface between the MCU and a serial I
Preliminary
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4
2
C-bus. It is capable of acting as
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