MAX1249AMJE Maxim Integrated, MAX1249AMJE Datasheet - Page 12

• Manufacturer Part Number: MAX1249AMJE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1249AMJE

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 64 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Package / Case: CDIP N
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 55 C
• Number Of Converters: 1
• Voltage Reference: External

In internal clock mode, the MAX1248/MAX1249 gener-
ate their own conversion clocks internally. This frees the
µP from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
Figure 7. External Clock Mode SSTRB Detailed Timing
Figure 8. Internal Clock Mode Timing
12
______________________________________________________________________________________
SSTRB
SSTRB
A/D STATE
DOUT
SCLK
SCLK
DIN
CS
CS
START
1
SEL2 SEL1 SEL0
2
3
IDLE
4
t
SDV
UNI/
BIP
5
SGL/
(f
DIF
ACQUISITION
SCLK
6
1.5µs
PD1 PD0
Internal Clock
= 2MHz)
7
8
(SHDN = FLOAT)
CONVERSION
7.5µs MAX
PD0 CLOCKED IN
t
CONV
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1248/MAX1249 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 9 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1248/MAX1249 at clock rates exceeding
2.0MHz if the minimum acquisition time, t
above 1.5µs.
9
MSB
B9
IDLE
10
t
SSTRB
B8
11
B7
12
18
LSB
B0
19
t
SSTRB
S1
20
S0
21
FILLED WITH
ZEROS
22
23
24
ACQ
t
STR
, is kept