AT89LP51ED2-20AAU Atmel, AT89LP51ED2-20AAU Datasheet - Page 152

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AT89LP51ED2-20AAU

Manufacturer Part Number
AT89LP51ED2-20AAU
Description
8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
Manufacturer
Atmel
Datasheet

Specifications of AT89LP51ED2-20AAU

Rohs
yes
Core
8051
Processor Series
AT89x
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
64 KB
Data Ram Size
256 B
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-44
Mounting Style
SMD/SMT
Data Rom Size
4 KB
Interface Type
2-Wire, SPI, UART
Number Of Programmable I/os
36
Number Of Timers
3
Program Memory Type
Flash
Factory Pack Quantity
160

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89LP51ED2-20AAU
Manufacturer:
Atmel
Quantity:
10 000
Figure 19-12. Format and States in Master Receiver Mode
19.6.3
152
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
AT89LP51RD2/ED2/ID2 Preliminary
Slave Receiver Mode
From master to slave
From slave to master
08h
S
SLA
In the Slave Receiver mode, a number of data bytes are received from a master transmitter. To
initiate the Slave Receiver mode, SSADR and SSCON must be initialized as follows:
The upper seven bits are the address to which the Two-wire Serial Interface will respond when
addressed by a master. If the LSB is set, the TWI will respond to the general call address (00h),
otherwise it will ignore the general call address.:
SSADR
Value
SSCON
Value
R
MR
CR2
S6
A or A
DATA
X
40h
48h
38h
68h
A
A
A
78h
Other master
Other master
SSIE
SA5
n
continues
continues
1
P
B0h
DATA
A
SA4
Device’s own Slave Address
STA
0
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
STO
SA3
50h
38h
To corresponding
states in slave mode
0
A
A
Other master
DATA
continues
SA2
SI
0
58h
A
SA1
AA
1
10h
P
R
S
SA0
CR1
X
SLA
3714A–MICRO–7/11
CR0
GC
X
X
W
R
MT

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