S9S12GA240F0VLH Freescale Semiconductor, S9S12GA240F0VLH Datasheet - Page 345
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S9S12GA240F0VLH
Manufacturer Part Number
S9S12GA240F0VLH
Description
16-bit Microcontrollers - MCU 16BIT 240KB FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GA240F0VLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
240 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12GA240F0VLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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8.4.7.2
If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the
TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the
tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only
on completion of the subsequent trace (see
requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and
TRIG simultaneously.
8.4.7.3
If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an
effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is
followed by a subsequent comparator channel match, it has no effect, since tracing has already started.
If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is
activated by the BGND and the breakpoint to SWI is suppressed.
8.4.7.3.1
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU
is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In
addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active,
the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to coincide
with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed.
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes
the BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the
monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow.
Freescale Semiconductor
0
1
1
DBGBRK
Breakpoints Generated Via The TRIG Bit
Breakpoint Priorities
0
1
X
1
1
DBG Breakpoint Priorities And BDM Interfacing
1
x
x
Table 8-42. Breakpoint Setup For CPU Breakpoints
(DBGC1[4])
BDM Bit
Table 8-43. Breakpoint Mapping Summary
X
X
0
1
1
MC9S12G Family Reference Manual, Rev.1.23
1
1
0
Table
Enabled
Terminate tracing and generate breakpoint immediately on trigger
BDM
X
X
1
0
1
8-42). If no tracing session is selected, breakpoints are
A breakpoint request occurs when Trace Buffer is full
Terminate tracing immediately on trigger
Active
BDM
X
X
0
1
0
Start Trace Buffer at trigger
Breakpoint to BDM
Breakpoint to SWI
Breakpoint to SWI
S12S Debug Module (S12SDBGV2)
No Breakpoint
No Breakpoint
Breakpoint
Mapping
347
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