MM912F634DV1AE Freescale Semiconductor, MM912F634DV1AE Datasheet - Page 250

• Manufacturer Part Number: MM912F634DV1AE
• Description: 16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
• Manufacturer: Freescale Semiconductor

Specifications of MM912F634DV1AE

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 4.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Functional Description and Application Information
4.32.3.2.5
This registers contains the trimmed value for the Internal Reference Clock
Table 328. 9S12I32PIMV1 TRIM Register High Byte (CRGTRIMH)
Table 329. 9S12I32PIMV1 Trim Register Low Byte (CRGTRIML)
Read: Anytime
Write: Anytime
Writing the CRGTRIMH or CRGTRIML register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register.
Table 330. CRGTRIMH and CRGTRIML Field Descriptions
4.32.3.2.6
Table 331. 9S12I32PIMV1 Test Register 0 (CRGTEST0)
This register is reserved for factory test. This register is not writable.
Read: Anytime
Write: Not possible
Freescale Semiconductor
8, 7, 6, 5, 4, 3,
0x0038
0x0039
0x003A
Reset
Reset
Reset
TRIM[8:0]
W
W
W
R
R
2, 1, 0
R
Field
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed
Internal Reference Frequency f
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed
Trim Bits for Internal Reference Clock
After System Reset, the factory programmed trim value is automatically loaded into this register, resulting in a Internal
Reference Frequency f
The TRIM[8:0] bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Decreasing the binary value in TRIM[8:0]
will increase the frequency, increasing the value will decrease the frequency.
Trimmed frequency must be in the allowed range for f
15
0
0
F
0
0
7
7
9S12I32PIMV1TRIM register (CRGTRIMH, CRGTRIML)
9S12I32PIMV1 Test Register 0 (CRGTEST0)
14
F
0
0
0
0
6
6
IREF_TRIM
IREF_TRIM
. See
13
F
0
0
5
5
0
0
.
Electrical Characteristics
Internal Reference Frequency f
12
0
0
F
0
0
4
4
FLLREF
TRIM[7:0]
Description
. See device electrical characteristics for details.
for value of f
S12S Clocks and Reset Generator (S12SCRGV1)
11
0
0
F
0
0
3
3
IREF_TRIM
IREF_TRIM
.
10
0
0
F
0
0
2
2
.
F
9
0
0
1
1
0
0
MM912F634
TRIM[8]
F
F
0
0
8
0
0
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