MAX11627EEE/V+T Maxim Integrated, MAX11627EEE/V+T Datasheet - Page 17

• Manufacturer Part Number: MAX11627EEE/V+T
• Description: Analog to Digital Converters - ADC 12-Bit 300ksps ADCs 4-Channel with FIFO and Internal Reference
• Manufacturer: Maxim Integrated

Specifications of MAX11627EEE/V+T

• Number Of Channels: 4
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Power Dissipation: 667 mW
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The MAX11626–MAX11629/MAX11632/MAX11633
power up with all blocks in shutdown, including the ref-
erence. All registers power up in state 00000000,
except for the setup register, which powers up in clock
mode 10 (CKSEL1 = 1)
Figures 4–7 illustrate the conversion timing for the
MAX11626–MAX11629/MAX11632/MAX11633. The
12-bit conversion result is output in MSB-first format
with four leading zeros. DIN data is latched into the ser-
ial interface on the rising edge of SCLK. Data on DOUT
transitions on the falling edge of SCLK. Conversions in
clock modes 00 and 01 are initiated by CNVST.
Conversions in clock modes 10 and 11 are initiated by
writing an input data byte to the conversion register.
Data output is binary.
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX11626–MAX11629/
MAX11632/MAX11633 then wake up, scan all request-
ed channels, store the results in the FIFO, and shut
down. After the scan is complete, EOC is pulled low
and the results are available in the FIFO. Wait until EOC
Figure 4. Clock Mode 00 Timing
CNVST
SCLK
DOUT
EOC
CS
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.
Performing Conversions in Clock Mode 00
Internally Timed Acquisitions and
______________________________________________________________________________________
Conversions Using CNVST
Power-Up Default State
Output Data Format
with FIFO and Internal Reference
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
MSB1
goes low before pulling CS low to communicate with
the serial interface. EOC stays low until CS or CNVST is
pulled low again.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using the
internal oscillator. See Figure 5 for clock mode 01 timing.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If the internal
reference needs to wake up, an additional 65µs is
required for the internal reference to power up.
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. The result is available on
DOUT once EOC has been pulled low.
Internally Timed Conversions with CNVST
12-Bit, 300ksps ADCs
Performing Conversions in Clock Mode 01
Externally Timed Acquisitions and
LSB1
MSB2
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