S9S12G64F0MLH Freescale Semiconductor, S9S12G64F0MLH Datasheet - Page 344
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S9S12G64F0MLH
Manufacturer Part Number
S9S12G64F0MLH
Description
16-bit Microcontrollers - MCU S12 Core,64k Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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S12S Debug Module (S12SDBGV2)
8.4.6
A tag follows program information as it advances through the instruction queue. When a tagged instruction
reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition.
Each comparator control register features a TAG bit, which controls whether the comparator match causes
a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is
enabled for tagged comparisons, the address stored in the comparator match address registers must be an
opcode address.
Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the
transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started.
Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when
the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is
generated immediately, before the tagged instruction is carried out.
R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected,
since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on
the type of access. Thus these bits are ignored if tagging is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
Tagging is disabled when the BDM becomes active.
8.4.7
It is possible to generate breakpoints from channel transitions to final state or using software to write to
the TRIG bit in the DBGC1 register.
8.4.7.1
Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for
tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the
instruction queue.
If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session
has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion
of the subsequent trace (see
immediately.
If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing
trigger alignment.
346
BRK
0
0
0
Breakpoints
Tagging
Breakpoints From Comparator Channels
TALIGN
0
0
1
Table 8-42. Breakpoint Setup For CPU Breakpoints
Table
DBGBRK
MC9S12G Family Reference Manual, Rev.1.23
8-42). If no tracing session is selected, breakpoints are requested
0
1
0
Fill Trace Buffer until trigger, then breakpoint request occurs
Fill Trace Buffer until trigger then disarm (no breakpoints)
Start Trace Buffer at trigger (no breakpoints)
Breakpoint Alignment
Freescale Semiconductor
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