S9S12GA192F0MLHR Freescale Semiconductor, S9S12GA192F0MLHR Datasheet - Page 379
S9S12GA192F0MLHR
Manufacturer Part Number
S9S12GA192F0MLHR
Description
16-bit Microcontrollers - MCU 16BIT192KFLASH 11264 RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GA192F0MLHR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
192 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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10.3.2.7
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
Freescale Semiconductor
0x003A
FM1, FM0
Reset
Field
5, 4
W
R
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is f
S12CPMU PLL Control Register (CPMUPLL)
0
0
7
Write to this register clears the LOCK and UPOSC status bits.
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
Figure 10-10. S12CPMU PLL Control Register (CPMUPLL)
0
0
6
MC9S12G Family Reference Manual, Rev.1.23
Table 10-7. CPMUPLL Field Descriptions
Table 10-8. FM Amplitude selection
FM1
FM1
0
5
0
0
1
1
0
1
0
1
FM0
NOTE
NOTE
FM0
0
4
Description
FM Amplitude /
FM off
±1%
±2%
±4%
S12 Clock, Reset and Power Management Unit (S12CPMU)
f
VCO
ref
0
0
3
divided by 16. See
Variation
0
0
2
Table 10-8
0
0
1
for coding.
0
0
0
381
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