MAX1204BMJP Maxim Integrated, MAX1204BMJP Datasheet - Page 8

• Manufacturer Part Number: MAX1204BMJP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1204BMJP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 66 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Package / Case: CDIP N
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 55 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1204 uses a successive-approximation con-
version technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to 3V
microprocessors (µPs). Figure 3 is the MAX1204 block
diagram.
Figure 4 shows the analog-to-digital converter’s
(ADC’s) analog comparator’s sampling architecture. In
single-ended mode, IN+ is internally switched to
CH0–CH7 and IN- is switched to GND. In differential
mode, IN+ and IN- are selected from pairs of CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels using Tables 3 and 4.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable with-
in ±0.5 LSB (±0.1 LSB for best results) with respect to
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
MAX1204
8
_______________Detailed Description
DOUT
DOUT
a. High-Z to V
3kΩ
3kΩ
a. V
OH
GND
GND
and V
OH
to High-Z
OL
to V
OH
Pseudo-Differential Input
C
C
LOAD
LOAD
b. High-Z to V
DOUT
DOUT
b. V
OL
+3.3V
+3.3V
to High-Z
OL
3kΩ
and V
3kΩ
C
GND
LOAD
C
GND
LOAD
OH
to V
OL
GND during a conversion. To do this, connect a 0.1µF
capacitor from IN- (of the selected analog input) to
GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C
sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). In single-ended mode, IN- is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(V
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Figure 3. Block Diagram
REFADJ
SHDN
IN
SCLK
GND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF
DIN
CS
+) - (V
18
19
17
10
13
12
11
1
2
3
4
5
6
7
8
REGISTER
IN
ANALOG
INPUT
SHIFT
INPUT
MUX
-)] from C
HOLD
REFERENCE
+2.44V
from the positive input (IN+) to the
CONTROL
T/H
LOGIC
HOLD
20k
A
+4.096V
IN
≈ 1.68
CLOCK
to the binary-weighted
CLOCK
INT
REF
ADC
SAR
OUT
MAX1204
REGISTER
OUTPUT
SHIFT
Maxim Integrated
HOLD
HOLD
14
9
15
16
20
. The
DOUT
SSTRB
V
V
V
as a
DD
L
SS