MAX1361MEUB-T Maxim Integrated, MAX1361MEUB-T Datasheet - Page 20

• Manufacturer Part Number: MAX1361MEUB-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1361MEUB-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 150 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: Serial (2-Wire, I2C, SMBus)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: uMAX
• Maximum Power Dissipation: 689.7 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V or External

4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
To disable alarming on a specific channel, set the lower
threshold to 0x800 and the upper threshold to 0x7FF for
bipolar mode, or set the lower threshold to 0x000 and
the upper threshold to 0xFFF for unipolar mode.
Select readback mode by setting CS3, CS2 to [1,1] in
the configuration byte. Begin a read operation to start
reading back monitor-setup data. Clock out delay bit
settings, INT_EN bit, and the lower and upper thresh-
olds programmed for each channel. Readback mode
follows exactly the same format as writing to the moni-
tor-setup data, with the exception of the first 4 alarm-
reset bits, which are always 1 (Table 13).
Reading in monitor mode reads back the alarm-status
register, latched-fault register, and current-conversion
results as shown in Table 14.
The MAX1361/MAX1362 register pointer loops back to
the beginning of the current-conversion result after
reading the last conversion result. Stop reading at any
time by asserting a STOP condition or NACK.
Note: The MAX1361/MAX1362 do not update the current-
conversion results register while reading in monitor mode.
Monitor mode resumes after a STOP condition or NACK.
Table 13. Readback-Mode Format
Table 14. Reading in Monitor-Mode Data Format
Table 15. Alarm-Status Register
0 = Not-alarm condition.
1 = Alarm condition.
Table 16. Latched-Fault and Current-
Conversion Register
20
1
ALARM-STATUS REGISTER
16-bit read
SCAN SPEED AND INT_EN
CH0 UP
1
AIN0
______________________________________________________________________________________
0/1
1
1 D2 D1 D0 INT_EN
8 bits
16-bit read
CH0 LOW
AIN1
0/1
Reading in Monitor Mode
16-bit read
16, 32, 48, or 64 bits (depends on CSO, CS1,
THRESHOLDS
CH1 UP
AIN2
24 bits
Readback Mode
0/1
AIN0
LATCHED-FAULT REGISTER
16-bit read
and SE/DIF)
MODE OR CS1, CS0 < 1)
(SKIP IF DIFFERENTIAL
CH1 LOW
AIN3
AIN1 THRESHOLDS
0/1
24 bits
The latched-fault register records a snapshot of the
alarming channel at the instance that a fault condition is
asserted. An alarm-status bit of 1 (Table 15) indicates a
fault, and the data in the latched-fault register of the
corresponding channel contains the conversion result
that caused the alarm to trip. Resetting alarms does not
clear the latched-fault register, thus the latched-fault
register contains valid data only if an alarm status bit is
high for the given channel.
The current-conversion register contains the most
recent conversion results. If the user attempts to read
past the last result of the current-conversion register,
the MAX1361/MAX1362 wraps back to the beginning of
the current-conversion result.
The latched-fault register and current-conversion regis-
ter follow the data format detailed in Tables 8 and 16.
Register length depends on the number of conversions
in one monitoring sequence. For example, when chan-
nel pairs 0/1 and channels 2/3 are monitored differential-
ly, there are only two conversion results to report. The
latched-fault register is 2 x 16 bits long, after which two
current-conversion results follow. Likewise, if CS0 and
CS1 limit the upper bound of the channel scan range
from CH0 to CH2 in single-ended mode, the latched-
fault register clocks out 3 x 16 bits of data followed by
the current-conversion results, also 3 x 16 bits.
CH2 UP
0/1
(SKIP IF CS1, CS0 < 2)
AIN2 THRESHOLDS
16, 32, 48, or 64 bits (depends on CSO, CS1,
CH2 LOW
24 bits
CURRENT-CONVERSION RESULTS
0/1
and SE/DIF)
CH3 UP
MODE OR CS1, CS0 < 3)
(SKIP IF DIFFERENTIAL
Alarm-Status Register
0/1
AIN3 THRESHOLDS
24 bits
CH3 LOW
0/1