MAX1415EUE Maxim Integrated, MAX1415EUE Datasheet - Page 20

• Manufacturer Part Number: MAX1415EUE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1415EUE

• Number Of Channels: 2
• Architecture: Sigma-Delta
• Conversion Rate: 0.5 KSPs
• Resolution: 16 bit
• Input Type: Differential
• Snr: No
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-16
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: - 45 C
• Number Of Converters: 1
• Voltage Reference: 1.75 V

To minimize gain errors in unbuffered mode, select a
source impedance less than the maximum values
shown in Figures 2 and 3. These are the maximum
external resistance/capacitance combinations allowed
before gain errors greater than 1 LSB are introduced in
unbuffered mode.
Enable the internal input buffer for a high source imped-
ance. This isolates the inputs from the sampling capaci-
tor and reduces the sampling-related gain error. When
using the internal buffer, limit the absolute input voltage
range to (V
up the gain and common-mode voltage range to mini-
mize linearity errors.
In unbuffered mode, the absolute analog input voltage
range is from (GND - 30mV) to (V
Electrical Characteristics section). In buffered mode,
the analog input voltage range is reduced to (GND +
50mV) to (V
modes, the differential analog input range (V
decreases at higher gains (see the Programmable Gain
Amplifier and Unipolar and Bipolar Modes sections).
The MAX1415/MAX1416 provide differential inputs,
REF+ and REF-, for an external reference voltage.
Connect the external reference directly across REF+ and
REF- to obtain the differential reference voltage, V
The common-mode voltage range for V
is between GND and V
nominal voltage, V
2.5V for the MAX1416.
The MAX1415/MAX1416 sample REF+ and REF- at
f
with an internal 10pF (typ for gain = 1) sampling capac-
itor in series with a 7kΩ (typ) switch on-resistance.
A PGA provides selectable levels of gain: 1, 2, 4, 8, 16,
32, 64, and 128. Bits G0, G1, and G2 in the setup reg-
ister control the gain (see
es, the value of the input sampling capacitor, C
also increases (see Table 5). The dynamic load pre-
sented to the analog inputs increases with clock fre-
quency and gain in unbuffered mode (see the Input
Buffers section and Figure 1).
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
20
CLKIN
______________________________________________________________________________________
/64 (CLKDIV = 0) or f
GND
DD
- 1.5V). In both buffered and unbuffered
+ 50mV) to (V
Programmable Gain Amplifier
REF
is 1.225V for the MAX1415 and
DD
Table 9). As the gain increas-
. For specified operation, the
Input Voltage Range
CLKIN
DD
DD
- 1.5V). Properly set
/128 (CLKDIV = 1)
+ 30mV) (see the
REF+
Reference
AIN+
and V
- V
SAMP
AIN-
REF-
REF
)
.
,
Figure 1. Unbuffered Analog Input Structure
Figure 2. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (1MHz)
Figure 3. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (2.4576MHz)
AIN(+)
AIN(-)
vs. MAXIMUM EXTERNAL CAPACITANCE (1MHz)
100
100
0.1
0.1
10
10
1
1
vs. MAXIMUM EXTERNAL CAPACITANCE
1
1
MAXIMUM EXTERNAL RESISTANCE
MAXIMUM EXTERNAL RESISTANCE
R
GAIN = 4
SW
GAIN = 8 TO 128
GAIN = 4
GAIN = 8 TO 128
EXTERNAL CAPACITANCE (pF)
EXTERNAL CAPACITANCE (pF)
(7kΩ TYP)
10
10
(2.4576MHz)
GAIN = 1
GAIN = 1
V
100
BIAS
100
GAIN = 2
GAIN = 2
C
TOTAL
C
TOTAL
IMPEDANCE
1000
1000
(7pF TYP FOR GAIN = 1)
HIGH-
INPUT
= C
SAMP
10,000
10,000
+ C
STRAY