S9S12GN32F0VLF Freescale Semiconductor, S9S12GN32F0VLF Datasheet - Page 182
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S9S12GN32F0VLF
Manufacturer Part Number
S9S12GN32F0VLF
Description
16-bit Microcontrollers - MCU 16-bit32k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN32F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
32 KB
Data Ram Size
2048 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
Available stocks
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Price
Company:
Part Number:
S9S12GN32F0VLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S12GN32F0VLFR
Manufacturer:
FREESCALE
Quantity:
20 000
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Port Integration Module (S12GPIMV1)
184
PAD5
PAD4
• 32 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the
• 20 TSSOP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when
• The ADC analog input channel signal AN5 and the related digital trigger input are mapped to this pin.
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin. If the SCI0 TXD signal is enabled the I/O state
• 20 TSSOP: The TIM channel 3 signal is mapped to this pin. The TIM forces the I/O state to be an output
• 20 TSSOP: The PWM channel 3 signal is mapped to this pin. If the PWM channel is enabled and
• 20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
• 20 TSSOP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin
• The ADC analog input channel signal AN4 and the related digital trigger input are mapped to this pin.
• 20 TSSOP: The SCI0 RXD signal is mapped to this pin. If the SCI0 RXD signal is enabled and routed
• 20 TSSOP: The TIM channel 2 signal is mapped to this pin. The TIM forces the I/O state to be an output
• 20 TSSOP: The PWM channel 2 signal is mapped to this pin. If the PWM channel is enabled and
• 20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to
output.
used with the ACMP function. The ACMP function has no effect on the output state. Refer to
NOTE/2-180
The ADC function has no effect on the output state. Refer to
will depend on the SCI0 configuration.
for a timer port associated with an enabled output compare.
routed here the I/O state is forced to output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
32 LQFP: ACMPO > GPO
20 TSSOP: TXD0 > IOC3 > PWM3 > GPO
Others: GPO
when used with the ACMP function. The ACMP function has no effect on the output state. Refer to
NOTE/2-180
The ADC function has no effect on the output state. Refer to
here the I/O state will be forced to input.
for a timer port associated with an enabled output compare.
routed here the I/O state is forced to output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
20 TSSOP: RXD0 > IOC2 > PWM2 > GPO
Others: GPO
ETRIG3-0”.
ETRIG3-0”.
for input buffer control.
for input buffer control.
Table 2-17. Port
MC9S12G Family Reference Manual,
AD
Pins AD7-0 (continued)
Rev.1.23
NOTE/2-180
NOTE/2-180
Section 2.6.4, “ADC External
Section 2.6.4, “ADC External
for input buffer control.
for input buffer control.
Freescale Semiconductor
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