MAX1111EEE-T Maxim Integrated, MAX1111EEE-T Datasheet - Page 7

• Manufacturer Part Number: MAX1111EEE-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1111EEE-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 50 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.048 V or External

Figure 1. Load Circuits for Enable Time
______________________________________________________________Pin Description
MAX1110
DOUT
1–4
5–8
10
11
12
13
14
15
16
17
18
19
20
a) High-Z to V
9
3kΩ
PIN
OH
MAX1111
DGND
and V
1–4
10
11
12
13
14
15
16
—
5
6
7
8
9
_______________________________________________________________________________________
OL
to V
OH
C
CH0–CH3
CH4–CH7
LOAD
REFOUT
SSTRB
NAME
DGND
REFIN
AGND
SHDN
DOUT
SCLK
COM
V
DIN
CS
DD
b) High-Z to V
DOUT
+2.7V, Low-Power, Multichannel,
Sampling Analog Inputs
Sampling Analog Inputs
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5 LSB.
Three-Level Shutdown Input. Normally high impedance. Pulling SHDN low shuts the
MAX1110/MAX1111 down to 10µA (max) supply current; otherwise, the devices are
fully operational. Pulling SHDN high shuts down the internal reference.
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.
Analog Ground
Digital Ground
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1110/
MAX1111 begin the A/D conversion and goes high when the conversion is done.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
Serial-Data Input. Data is clocked in at SCLK’s rising edge. The voltage at DIN can
exceed V
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance. The voltage at CS can exceed V
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%). The voltage at
SCLK can exceed V
Positive Supply Voltage, 2.7V to 5.5V
+3V
OL
and V
3kΩ
C
DGND
LOAD
OH
DD
to V
(up to 5.5V).
OL
DD
(up to 5.5V).
Figure 2. Load Circuits for Disable Time
DOUT
3kΩ
FUNCTION
a) V
Serial 8-Bit ADCs
DGND
OH
to High-Z
C
LOAD
DOUT
DD
b) V
(up to 5.5V).
OL
+3V
to High-Z
3kΩ
C
DGND
LOAD
7