MAX1444EHJ/V+T Maxim Integrated, MAX1444EHJ/V+T Datasheet - Page 14

• Manufacturer Part Number: MAX1444EHJ/V+T
• Description: Analog to Digital Converters - ADC 10-Bit 40Msps 3.0V Low-Power ADC with Internal Reference
• Manufacturer: Maxim Integrated

Specifications of MAX1444EHJ/V+T

• Number Of Channels: 1
• Architecture: Pipeline
• Conversion Rate: 40 MSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: 59.5 dB
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Power Dissipation: 1495.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.024 V

10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
Figure 6 shows the relationship between the clock
input, analog input, and data output. The MAX1444
samples at the falling edge of the input clock. Output
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 5 shows the relationship between the input clock
parameters and the valid output data.
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal refer-
ence provides a V
purposes. The input is buffered and then split to a volt-
age follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associ-
ated with high-speed op amps. The user may select the
R
to suit a particular application. For the application in
Figure 7, an R
tive load to prevent ringing and oscillation. The 22pF
C
14
Figure 6. System and Output Timing Diagram
__________Applications Information
ISO
IN
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
capacitor acts as a small bypassing capacitor.
______________________________________________________________________________________
and C
IN
values to optimize the filter performance
ISO
System Timing Requirements
DD
of 50Ω is placed before the capaci-
/2 output voltage for level shifting
t
AD
t
DO
N - 6
N
N - 5
N + 1
N - 4
N + 2
5.5 CLOCK-CYCLE LATENCY
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1444 for
optimum performance. Connecting the transformer’s
center tap to COM provides a V
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1444 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
Figure 9 shows an AC-coupled, single-ended applica-
tion. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
N - 3
N + 3
t
CL
Single-Ended AC-Coupled Input Signal
t
CH
N - 2
N + 4
Using Transformer Coupling
N - 1
N + 5
DD
N
N + 6
/2 DC level shift to
N + 1
N + 7