MAX195BEPE Maxim Integrated, MAX195BEPE Datasheet - Page 10

• Manufacturer Part Number: MAX195BEPE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX195BEPE

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 85 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 5 V

16-Bit, 85ksps ADC with 10µA Shutdown
10
Figure 8. MAX195 in the Simplest Operating Configuration
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
CONVERSION
10 F
+5V
______________________________________________________________________________________
CLOCK
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0)
NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
(CASE 3)
(CASE 2)
(CASE 1)
DOUT
SCLK
SCLK
SCLK
EOC
CS
1
2
3
4
5
6
7
8
0.1 F
BP/UP/
SHDN
CLK
SCLK
VDDD
DOUT
DGND
EOC
CS
MAX195
t
CONV
t
DV
RESET
VDDA
AGND
CONV
VSSD
VSSA
REF
AIN
t
CSS
MSB
B15
16
15
14
13
12
11
10
9
B14
0.1 F
t
SD
ANALOG
INPUT
REFERENCE
(0V TO VDDA)
B13
10 F
-5V
B12
B11
Data is clocked out on SCLK’s falling edge. Clock
data in on SCLK’s rising edge or, for clock speeds
above 2.5MHz, on the following falling edge to meet
the maximum SCLK-to-DOUT timing specification
(Figure 7). The maximum SCLK speed is 5MHz. See
the Operating Modes and SPI/QSPI Interfaces section
for additional information. When the conversion clock
is near its maximum (1.7MHz), reading the data after
each conversion (during the acquisition time) results
in lower throughput (about 70ksps max) than reading
the data during conversions, because it takes longer
than the minimum input acquisition time (four cycles
at 1.7MHz) to clock 16 data bits at 5Mbps. After the
data has been clocked in, leave some time (about
1µs) for any coupled noise on AIN to settle before
beginning the next conversion.
Whichever method is chosen for reading the data, con-
versions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX195 in its simplest
operational configuration.
B3
B2
B1
LSB
B0
t
CSH
t
DH