LCMXO640C-4F256I Lattice, LCMXO640C-4F256I Datasheet - Page 95
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LCMXO640C-4F256I
Manufacturer Part Number
LCMXO640C-4F256I
Description
CPLD - Complex Programmable Logic Devices Use LCMXO640C-4FT256
Manufacturer
Lattice
Datasheet
1.LCMXO1200C-5TN100C.pdf
(96 pages)
Specifications of LCMXO640C-4F256I
Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
550 MHz
Delay Time
4.2 ns
Number Of Programmable I/os
159
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Package / Case
FPBGA
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
17 mA
Supply Voltage - Max
3.465 V
Supply Voltage - Min
1.71 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640C-4F256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
August 2006
April 2006
May 2006
(cont.)
Date
Version
(cont.)
02.0
02.1
02.2
Ordering Information
Pinout Information
Pinout Information
DC and Switching
Characteristics
Architecture
Section
Multiple
(cont.)
“Top View of the MachXO1200 Device” figure updated.
“Top View of the MachXO640 Device” figure updated.
“Top View of the MachXO256 Device” figure updated.
“Slice Diagram” figure updated.
Slice Signal Descriptions table updated.
Routing section updated.
sysCLOCK Phase Lockecd Loops (PLLs) section updated.
PLL Diagram updated.
PLL Signal Descriptions table updated.
sysMEM Memory section has been updated.
PIO Groups section has been updated.
PIO section has been updated.
MachXO PIO Block Diagram updated.
Supported Input Standards table updated.
MachXO Configuration and Programming diagram updated.
Recommended Operating Conditions table - footnotes updated.
MachXO256 and MachXO640 Hot Socketing Specifications - footnotes
updated.
Added MachXO1200 and MachXO2280 Hot Socketing Specifications
table.
DC Electrical Characteristics, footnotes have been updated.
Supply Current (Sleep Mode) table has been updated, removed "4W"
references. Footnotes have been updated.
Supply Current (Standby) table and associated footnotes updated.
Intialization Supply Current table and footnotes updated.
Programming and Erase Flash Supply Current table and associated
footnotes have been updatd.
Register-to-Register Performance table updated (rev. A 0.19).
MachXO External Switching Characteristics updated (rev. A 0.19).
MachXO Internal Timing Parameters updated (rev. A 0.19).
MachXO Family Timing Adders updated (rev. A 0.19).
sysCLOCK Timing updated (rev. A 0.19).
MachXO "C" Sleep Mode Timing updated (A 0.19).
JTAG Port Timing Specification updated (rev. A 0.19).
Test Fixture Required Components table updated.
Signal Descriptions have been updated.
Pin Information Summary has been updated. Footnote has been
added.
Power Supply and NC Connection table has been updated.
Logic Signal Connections have been updated (PCLKTx_x --> PCLKx_x)
Removed "4W" references.
Added 256-ftBGA Ordering Part Numbers for MachXO640.
Removed [LOC][0]_PLL_RST from Signal Description table.
PCLK footnote has been added to all appropriate pins.
Removed 256 fpBGA information for MachXO640.
7-2
Change Summary
MachXO Family Data Sheet
Revision History