M4A3-256/160-12YNI Lattice, M4A3-256/160-12YNI Datasheet - Page 34
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
M4A3-256/160-12YNI
Manufacturer Part Number
M4A3-256/160-12YNI
Description
CPLD - Complex Programmable Logic Devices Use ispMACH 4000V
Manufacturer
Lattice
Datasheet
1.M4A5-19296-10VNI.pdf
(62 pages)
Specifications of M4A3-256/160-12YNI
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
256
Maximum Operating Frequency
182 MHz
Delay Time
12 ns
Number Of Programmable I/os
160
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
PQFP-208
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
120
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A3-256/160-12YNI
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192
34
Detail A
Block C
Block F
Block G
Block J
16
16
16
16
24
24
24
24
16
16
16
16
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
Output Switch
AND Logic Array
Output Switch
Output Switch
AND Logic Array
Output Switch
AND Logic Array
Macrocells
Macrocells
Macrocells
Macrocells
I/O Cells
Matrix
I/O Cells
I/O Cells
Matrix
I/O Cells
Matrix
72 X 90
Matrix
72 X 90
Block K
Block B
72 X 90
72 X 90
16
16
16
16
8
8
8
8
8
36
8
36
36
16
16
8
36
16
16
8
8
8
8
8
4
4
4
4
4
4
4
4
4
4
4
4
Block D
Block E
Block H
Block I
16
16
16
16
24
24
24
24
16
16
16
16
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
Output Switch
AND Logic Array
AND Logic Array
Output Switch
Output Switch
Output Switch
Macrocells
Macrocells
Macrocells
Macrocells
I/O Cells
I/O Cells
I/O Cells
Matrix
I/O Cells
Matrix
Matrix
72 X 90
Matrix
72 X 90
Block A
72 X 90
72 X 90
Block L
16
16
16
16
8
8
8
8
8
36
36
16
16
8
8
36
36
16
16
8
ispMACH 4A Family
8
8
8
8
4
4
4
4
4
4
4
4
4
4
4
4
Repeat Detail A
4
CLK0–CLK3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
AND Logic Array
AND Logic Array
Output Switch
Output Switch
Output Switch
Output Switch
Block HX
I/O Cells
Macrocells
I/O Cells
Macrocells
72 X 90
72 X 90
Macrocells
I/O Cells
72 X 90
72 X 90
Macrocells
I/O Cells
Block M
16
16
36
36
16
16
16
16
36
36
16
16
Matrix
Matrix
8
8
8
8
Matrix
Matrix
8
8
8
8
16
16
16
16
24
24
24
24
16
16
16
16
Block EX
Block DX
Block AX
Block P
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
AND Logic Array
AND Logic Array
Output Switch
Output Switch
Output Switch
Output Switch
Block GX
I/O Cells
Macrocells
I/O Cells
I/O Cells
Macrocells
I/O Cells
Macrocells
72 X 90
72 X 90
Macrocells
72 X 90
72 X 90
Block N
16
16
36
36
16
16
16
16
36
36
16
16
Matrix
8
Matrix
8
8
Matrix
8
Matrix
8
8
8
8
16
16
16
16
24
24
24
24
16
16
16
16
Block FX
Block CX
Block BX
Block O
17466G-067