S9S12G96F0MLF Freescale Semiconductor, S9S12G96F0MLF Datasheet - Page 301
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S9S12G96F0MLF
Manufacturer Part Number
S9S12G96F0MLF
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0MLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Figure 7-9
there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit
time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives
it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting
the bit time.
Freescale Semiconductor
Start of Bit Time
Start of Bit Time
Speedup Pulse
Target System
Target System
(Target MCU)
(Target MCU)
BDM Clock
BDM Clock
BKGD Pin
BKGD Pin
Perceived
BKGD Pin
BKGD Pin
Drive and
Perceived
Speedup
Drive to
Drive to
Pulse
Host
Host
shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,
Figure 7-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
High-Impedance
MC9S12G Family Reference Manual, Rev.1.23
10 Cycles
10 Cycles
R-C Rise
10 Cycles
10 Cycles
High-Impedance
Host Samples
High-Impedance
Host Samples
BKGD Pin
BKGD Pin
Background Debug Module (S12SBDMV1)
Speedup Pulse
High-Impedance
Next Bit
Earliest
Start of
Next Bit
Earliest
Start of
303
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