MAX11624EEG+T Maxim Integrated, MAX11624EEG+T Datasheet
MAX11624EEG+T
Specifications of MAX11624EEG+T
Related parts for MAX11624EEG+T
MAX11624EEG+T Summary of contents
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... SPI-/QSPI-/MICROWIRE-Compatible Interface o Small Packages 16-Pin QSOP (MAX11618–MAX11621) 24-Pin QSOP (MAX11624/MAX11625) PART MAX11618EEE+T MAX11619EEE+T MAX11620EEE+T MAX11621EEE+T MAX11624EEG+T MAX11625EEG+T Note: All devices are specified over the -40°C to +85°C operating temperature range. + Denotes a lead(Pb)-free/RoHS-compliant package. Features DD Ordering Information NUMBER SUPPLY ...
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ADCs with FIFO and Internal Reference ABSOLUTE MAXIMUM RATINGS V to GND ..............................................................-0.3V to +6V DD CS, SCLK, DIN, EOC, DOUT to GND.........-0. AIN0–AIN14, CNVST/AIN_, REF to GND ...........................................-0. Maximum Current into Any Pin............................................50mA ...
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ELECTRICAL CHARACTERISTICS (continued 2.7V to 3.6V (MAX11619/MAX11621/MAX11625 300kHz 4.8MHz (external clock, 50% duty cycle), V SAMPLE SCLK (MAX11618/MAX11620/MAX11624 PARAMETER SYMBOL CONVERSION RATE Power-Up Time Acquisition Time t ACQ Conversion Time ...
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ADCs with FIFO and Internal Reference ELECTRICAL CHARACTERISTICS (continued 2.7V to 3.6V (MAX11619/MAX11621/MAX11625 300kHz 4.8MHz (external clock, 50% duty cycle), V SAMPLE SCLK (MAX11618/MAX11620/MAX11624 PARAMETER SYMBOL ...
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TIMING CHARACTERISTICS (Figure 2.7V to 3.6V (MAX11619/MAX11621/MAX11625 300kHz 4.8MHz (50% duty cycle), V SAMPLE SCLK (MAX11618/MAX11620/MAX11624 PARAMETER SYMBOL SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Fall ...
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ADCs with FIFO and Internal Reference ( (MAX11619/MAX11621/MAX11625 +25°C, unless otherwise noted.) A DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 MAX11619/MAX11621/ -0.3 MAX11625 -0 ...
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+25°C, unless otherwise noted.) A SUPPLY CURRENT vs. SUPPLY VOLTAGE 2000 INTERNAL REFERENCE 1800 1600 1400 1200 EXTERNAL REFERENCE 1000 800 600 MAX11619/MAX11621/ 400 MAX11625 200 f = 300ksps SAMPLE 0 2.7 ...
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ADCs with FIFO and Internal Reference ( (MAX11619/MAX11621/MAX11625 +25°C, unless otherwise noted.) A INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 4.099 MAX11618/MAX11620/ MAX11624 4.098 4.097 4.096 4.095 4.094 4.75 ...
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+25°C, unless otherwise noted.) A OFFSET ERROR vs. TEMPERATURE 1.0 0.6 0.2 -0.2 MAX11618/MAX11620/ -0.6 MAX11624 f = 300ksps SAMPLE -1.0 -40 - TEMPERATURE (°C) GAIN ERROR vs. SUPPLY ...
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ADCs with FIFO and Internal Reference TOP VIEW + AIN0 1 AIN1 2 AIN2 3 AIN3 4 AIN4 (N.C.) 5 AIN5 (N.C.) 6 AIN6 (N.C.) 7 AIN7/(CNVST MAX11618/MAX11619 ONLY PIN MAX11618 MAX11620 MAX11624 MAX11619 MAX11621 MAX11625 ...
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CS t CSS0 t CL SCLK DIN t DOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK CNVST AIN0 AIN1 AIN15 REF Figure 2. Functional Diagram Detailed Description The MAX11618–MAX11621/MAX11624/MAX11625 are low-power, serial-output, multichannel ...
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ADCs with FIFO and Internal Reference Converter Operation The MAX11618–MAX11621/MAX11624/MAX11625 ADCs use a successive-approximation register (SAR) conversion technique and an on-chip T/H block to con- vert voltage signals into a 10-bit digital result. This single- ended configuration supports ...
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True Differential Analog Input T/H The equivalent circuit of Figure 3 shows the MAX11618–MAX11621/MAX11624/MAX11625s’ input architecture. In track mode, a positive input capacitor is connected to AIN0–AIN15. A negative input capacitor is connected to GND. For external T/H timing, use ...
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ADCs with FIFO and Internal Reference Conversion Register Select active analog input channels per scan and scan modes by writing to the conversion register. Table 2 details channel selection and the four scan modes. Request a scan by ...
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Table 3. Setup Register* BIT NAME BIT — 7 (MSB) Set to zero to select setup register. — 6 Set select setup register. Clock mode and CNVST configuration. Resets power-up. CKSEL1 5 Clock mode ...
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ADCs with FIFO and Internal Reference Table 4. Averaging Register* BIT NAME BIT — 7 (MSB) Set select averaging register. — 6 Set select averaging register. — 5 Set ...
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Power-Up Default State The MAX11618–MAX11621/MAX11624/MAX11625 power up with all blocks in shutdown, including the ref- erence. All registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (CKSEL1 = 1). Output Data ...
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ADCs with FIFO and Internal Reference CNVST (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN CS SCLK DOUT EOC THE CONVERSION ...
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DIN (ACQUISITION1) CS SCLK DOUT EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles pulsed high ...
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ADCs with FIFO and Internal Reference Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2011 Maxim Integrated Products ...