ispLSI 2128A-100LT176 Lattice, ispLSI 2128A-100LT176 Datasheet - Page 2
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ispLSI 2128A-100LT176
Manufacturer Part Number
ispLSI 2128A-100LT176
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet
1.ISPLSI_2128A-80LT176I.pdf
(13 pages)
Specifications of ispLSI 2128A-100LT176
Memory Type
EEPROM
Number Of Macrocells
128
Maximum Operating Frequency
100 MHz
Delay Time
13 ns
Number Of Programmable I/os
128
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-176
Mounting Style
SMD/SMT
Factory Pack Quantity
200
Supply Current
325 mA
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
The device also has 128 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2128 and 2128A device contains four Megablocks.
Figure 1. ispLSI 2128/A Functional Block Diagram
Functional Block Diagram
MODE/IN 1
SCLK/IN 0
RESET
GOE 0
GOE 1
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
ispEN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
Megablock
A0
A1
A2
A3
A4
A5
A6
A7
B0
Output Routing Pool (ORP)
D7
B1
Output Routing Pool (ORP)
D6
B2
D5
B3
Input Bus
Routing
Global
(GRP)
Pool
D4
2
Input Bus
B4
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128 and 2128A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Output Routing Pool (ORP)
Specifications ispLSI 2128/A
D3
Output Routing Pool (ORP)
B5
D2
B6
D1
B7
D0
C7
C6
C5
C4
C3
C2
C1
C0
0139(10A)/2128
IN 5
IN 4
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64