dsPIC33FJ06GS001-I/P Microchip Technology, dsPIC33FJ06GS001-I/P Datasheet - Page 27
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dsPIC33FJ06GS001-I/P
Manufacturer Part Number
dsPIC33FJ06GS001-I/P
Description
Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 6 KB FL 256Bytes RAM SMPS
Manufacturer
Microchip Technology
Datasheet
1.DSPIC33FJ09GS302-ISP.pdf
(52 pages)
Specifications of dsPIC33FJ06GS001-I/P
Rohs
yes
Core
dsPIC33F
Data Bus Width
16 bit
Program Memory Size
6 KB
Data Ram Size
256 B
Device Million Instructions Per Second
40 MIPs
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Package / Case
PDIP-18
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ06GS001-I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
5.0
5.1
If it is determined that the programming executive is not
present in executive memory (as described in
Section 4.2 “Confirming the Presence of the
Programming
executive must be programmed to executive memory.
Figure 5-1
programming
executive memory. First, ICSP mode must be entered
and
programming executive is programmed and verified.
Lastly ICSP mode is exited.
FIGURE 5-1:
© 2011 Microchip Technology Inc.
Note:
dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
executive
PROGRAMMING THE
PROGRAMMING EXECUTIVE
TO MEMORY
Overview
The Programming Executive (PE) can be
located within the following folder within
your installation of MPLAB
...\Microchip\MPLAB IDE\REAL ICE,
and then selecting the Hex PE file,
RIPE_01d_xxxxxx.hex.
shows
the
Programming Executive
Programming Executive
Executive”),
memory
Enter ICSP mode
Erase Executive
Exit ICSP mode
Read/Verify the
Program the
the
programming
HIGH-LEVEL
PROGRAMMING
EXECUTIVE
PROGRAMMING FLOW
Memory
Start
End
high
is
erased,
the
level
®
executive
IDE:
programming
process
then
into
the
of
5.2
The procedure for erasing executive memory is similar
to that of erasing program memory and is shown in
Figure
initializing the TBLPAG register to the beginning of
executive memory; 0x80, and then executing the
programming cycle.
Table 5-1
Erasing executive memory.
FIGURE 5-2:
Note:
5-2. It consists of setting NVMCON to 0x404F,
Erasing Executive Memory
illustrates the ICSP programming process for
Initialize the TBLPAG register to 0x80
The
always
programmed, as described in
Write 0x404F to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
programming
be
ERASE FLOW
Start
End
erased
executive
DS70659B-page 27
before
Figure
it
must
5-1.
is