MAX1464AAI-T Maxim Integrated, MAX1464AAI-T Datasheet - Page 15

• Manufacturer Part Number: MAX1464AAI-T
• Description: Digital Signal Processors & Controllers - DSP, DSC Low-Pwr/Nse MultiCh Sensor Signal Prcssr
• Manufacturer: Maxim Integrated
• Series: MAX1464r

Specifications of MAX1464AAI-T

• Data Bus Width: 16 bit
• Program Memory Size: 4 KB, 128 B
• Maximum Clock Frequency: 5.3 MHz
• Number Of Programmable I/os: 2
• Operating Supply Voltage: 5 V
• Interface Type: SPI
• On-chip Adc: Yes
• Processor Series: MAX1464
• Product: DSPs
• Program Memory Type: Flash

Single-ended inputs can be converted by either channel
1 or 2 by initiating a conversion on the appropriate chan-
nel with the SE[3:0] bits set to the desired single-ended
input (Table 7). Several of the single-ended signals are
converted with a fixed gain. The reduced gain of 0.7V/V
allows signals at or near the supply rails to be converted
without concern of saturation. Other single-ended signals
can be converted with the full selectable PGA gain range.
The gain of the differential inputs and several
single-ended inputs can be set to values between
0.99V/V to 244V/V as shown in Table 14. The PGA bits
are set in ADC_Config_nA where n = 1, 2, or T. The gain
setting must be selected prior to initiating a conversion.
The ADC conversion time is a function of the selected
resolution, ADC clock (f
cy (f
bits in the ADC_Config_nA (where n = 1, 2, or T) register
Figure 4. ADC Module
CLK
). The resolution can be selected from 9 bits to 16
ADC Conversion Time and Resolution
TEMPERATURE
______________________________________________________________________________________
SENSOR
INP1
INM1
INP2
INM2
ADC
Programmable-Gain Amplifier
V
SS
), and system clock frequen-
Low-Power, Low-Noise Multichannel
M
U
X
NO.
1
2
3
4
5
6
7
8
9
REF
V
OUTnSM
OUTnLG
V
V
DACnOUT VIA OUTnSM
DACnOUT VIA OUTnLG
INPn
INMn
BG
DD
SS
SINGLE-ENDED
PGA
Sensor Signal Processor
by bits RESn[2:0]. The lower resolution settings (9 bit)
convert faster than the higher resolution settings (16 bit).
The ADC clock f
clock f
from 4 to 512, producing a range of f
down to 7.8125kHz when f
Other values of f
f
Systems operating with very low power consumption
benefit from the reduced f
speeds require less operating current. Systems operat-
ing from a larger power consumption budget can use
the highest f
mance over power performance.
The ADC conversion times for various resolution and
clock-rate settings are summarized in Table 17. The
conversion time is calculated by the formula:
ADC
t
CONVERT
. See Tables 15 and 16.
CLK
ADC
by a prescalar divisor. The divisor can be set
ADC
= (no. of f
f
ADC
ADC
VBG
CLK
clock rate to improve speed perfor-
is derived from the primary system
produce other scaled values of
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
ADC
V
2 x V
4 x V
ADC
CLK
DD
clocks per conversion) /
ADC_Config_1A
ADC_Config_1B
ADC_Config_2A
ADC_Config_2B
ADC_Config_TA
ADC_Config_TB
REF
BG
ADC_Control
ADC_Data_1
ADC_Data_2
ADC_Data_T
clock rate. Slower clock
is operating at 4.0MHz.
ADC
from 1MHz
15