LC4256C-75FTN256AC Lattice, LC4256C-75FTN256AC Datasheet - Page 9
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LC4256C-75FTN256AC
Manufacturer Part Number
LC4256C-75FTN256AC
Description
CPLD - Complex Programmable Logic Devices 256MC 128 I/O ispJTAG 1.8V 7.5ns
Manufacturer
Lattice
Datasheet
1.LC4384C-5FTN256C.pdf
(99 pages)
Specifications of LC4256C-75FTN256AC
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
256
Maximum Operating Frequency
178.57 MHz
Delay Time
7.5 ns
Number Of Programmable I/os
160
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
FTBGA
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
80
Factory Pack Quantity
450
Supply Current
2.5 mA
Supply Voltage - Max
1.95 V
Supply Voltage - Min
1.65 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4256C-75FTN256AC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists
of the following elements:
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.
Table 6. ORP Combinations for I/O Blocks with 8 I/Os
• Output Routing Multiplexers
• OE Routing Multiplexers
• Output Routing Pool Bypass Multiplexers
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
From PTOE
5-PT Fast Path
From Macrocell
Output Routing Multiplexer
OE Routing Multiplexer
9
Available Macrocells
ispMACH 4000V/B/C/Z Family Data Sheet
ORP
Bypass
Multiplexer
OE
Output
To I/O
To I/O
Cell
Cell