MAX1302AEUG+T Maxim Integrated, MAX1302AEUG+T Datasheet - Page 14

• Manufacturer Part Number: MAX1302AEUG+T
• Description: Analog to Digital Converters - ADC 16Bit, 8Ch, 4.096V Multi-In Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1302AEUG+T

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 115 kSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 1111.1 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

To maintain a low-noise environment, the MAX1302
provides separate power supplies for each section of
circuitry. Table 1 shows the four separate power sup-
plies. Achieve optimal performance using separate
AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD
together as close to the device as possible for a conve-
nient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close as pos-
sible to the device. Bypass each supply to the corre-
sponding ground using a 0.1µF capacitor (Table 1). If
significant low-frequency noise is present, add a 10µF
capacitor in parallel with the 0.1µF bypass capacitor.
The MAX1302 ADC features a fully differential, succes-
sive-approximation register (SAR) conversion tech-
nique and an on-chip T/H block to convert voltage
signals into a 16-bit digital result. Both single-ended
and differential configurations are supported with pro-
grammable unipolar and bipolar signal ranges.
8-Channel, ±V
Serial 16-Bit ADC
Table 1. MAX1302 Power Supplies and Bypassing
Table 2. Analog Input Configuration Byte
14
NUMBER
SUPPLY/GROUND
BIT
______________________________________________________________________________________
DVDDO/DGNDO
7
6
5
4
3
2
1
0
AVDD2/AGND2
AVDD1/AGND1
DVDD/DGND
POWER
DIF/SGL
START
NAME
C2
C1
C0
R2
R1
R0
Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
SUPPLY VOLTAGE
Converter Operation
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
RANGE (V)
2.7 to 5.25
REF
Power Supplies
Multirange Inputs,
TYPICAL SUPPLY
CURRENT (mA)
17.5
0.2
3.0
0.9
The MAX1302 features a switched-capacitor T/H archi-
tecture that allows the analog input signal to be stored as
charge on sampling capacitors. See Figures 2, 3, and 4
for T/H timing and the sampling instants for each operat-
ing mode. The MAX1302 analog input circuitry buffers
the input signal from the sampling capacitors, resulting
in a constant analog input impedance with varying input
voltage (Figure 5).
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 6kΩ input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
V
voltage:
V
SJ
SJ
DESCRIPTION
, is a function of the channel’s input common-mode
=
⎛
⎜
⎝
Digital I/O
Analog Circuitry
Analog Circuitry
Digital Control Logic and
Memory
R
1
CIRCUIT SECTION
R
+
1
R
2
⎞
⎟ ×
⎠
2 375
.
Track-and-Hold Circuitry
V
Analog Input Circuitry
+
⎛
⎜
⎝
1
0.1µF to DGNDO
0.1µF to AGND2
0.1µF to AGND1
0.1µF to DGND
+
⎛
⎜
⎝
R
1
BYPASSING
R
+
1
R
2
⎞
⎟
⎠
⎞
⎟ ×
⎠
V
CM