IS45S16400F-5BLA1-TR ISSI, IS45S16400F-5BLA1-TR Datasheet - Page 8

• Manufacturer Part Number: IS45S16400F-5BLA1-TR
• Description: DRAM 64M (4Mx16) 200MHz Automotive Temp
• Manufacturer: ISSI

Specifications of IS45S16400F-5BLA1-TR

• Product Category: DRAM
• Rohs: yes
• Data Bus Width: 16 bit
• Package / Case: TFBGA-54
• Memory Size: 64 Mbit
• Maximum Clock Frequency: 200 MHz
• Access Time: 6 ns, 5 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1500

IS42S16400F
IS45S16400F
8
TRUTH TABLE – COMMANDS AND DQM OPERATION
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
FUNCTION
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank/column, start READ burst)
WRITE (Select bank/column, start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
auto precharge; BA0, BA1 determine which bank is being read from or written to.
(2)
(8)
(8)
(6,7)
(3)
(4)
(4)
(5)
L
L
CS
—
—
H
L
L
L
L
L
L
RAS
—
—
H
H
H
H
X
L
L
L
L
CAS
—
—
X
H
H
H
H
L
L
L
L
Integrated Silicon Solution, Inc. — www.issi.com
(1)
WE
—
—
H
H
H
H
X
L
L
L
L
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
(8)
(8)
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
—
—
X
X
X
X
High-Z
12/01/2011
Active
Active
Valid
DQs
X
X
X
X
X
X
X
Rev. I