ISL26134AVZ-T7A Intersil, ISL26134AVZ-T7A Datasheet - Page 14

• Manufacturer Part Number: ISL26134AVZ-T7A
• Description: Analog to Digital Converters - ADC ISL26134AVZ LW-NOISE 24BIT DELTASIGMA ADC
• Manufacturer: Intersil

Specifications of ISL26134AVZ-T7A

• Product Category: Analog to Digital Converters - ADC
• Rohs: yes
• Number Of Channels: 4
• Architecture: Sigma-Delta
• Conversion Rate: 80 sps
• Resolution: 24 bit
• Input Type: Differential
• Snr: No
• Interface Type: Serial (2-Wire)
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 105 C
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 68 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

FIGURE 26. 10Sps: FREQUENCY RESPONSE OUT TO 100Hz
FIGURE 27. 10Sps: 50/60Hz NOISE REJECTION, 45Hz TO 65Hz
A0, A1, SPEED, Gain1, Gain0
-100
-150
PARAMETER
-100
-120
-130
-140
-150
-110
-50
SDO/RDY
-50
-60
-70
-80
-90
0
45
0
t1
t
S
10
20
50
30
FREQUENCY (Hz)
FREQUENCY (Hz)
14
40
50
DATA RATE = 10Sps
55
DATA RATE = 10 SPS
DATA RATE = 10Sps
FIGURE 28. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
60
Settling time
70
A0, A1, SPEED, Gain1, Gain0 change
60
80
ISL26132, ISL26134
90 100
(f
t
S
CLK
DESCRIPTION
set-up time
65
TABLE 8. SETTLING TIME
= 4.9152MHz)
SPEED = 1
SPEED = 0
Serial Clock Input (SCLK)
The serial clock input is provided with hysteresis to minimize
false triggering. Nevertheless, care should be taken to ensure
reliable clocking.
Filter Settling Time and ADC Latency
Whenever the analog signal into the ISL26132, ISL26134
converters is changed, the effects of the digital filter must be
taken into account. The filter takes four data ready periods for
the output code to fully reflect a new value at the analog input. If
the multiplexer control input is changed, the modulator and the
digital filter are reset, and the device uses four data ready
periods to fully settle to yield a digital code that accurately
represents the analog input. Therefore, from the time the control
inputs for the multiplexer are changed until the SDO/RDY goes
low, four data ready periods will elapse. The settling time delay
after a multiplexer channel change is listed in Table 8 for the
converter operating in continuous conversion mode.
t
1
MIN
404
40
54
MAX
405
50
55
September 9, 2011
UNITS
ms
ms
µs
FN6954.1