MAX6909EO33 Maxim Integrated, MAX6909EO33 Datasheet - Page 6

• Manufacturer Part Number: MAX6909EO33
• Description: Real Time Clock
• Manufacturer: Maxim Integrated
• Series: MAX6909, MAX6910r

Specifications of MAX6909EO33

• Function: Clock, Calendar, Watchdog Timekeeper, NV SRAM Control
• Rtc Bus Interface: Serial
• Time Format: HH
• Rtc Memory Size: 31 B
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-20

I
Supervisor and NV RAM Controller
AC ELECTRICAL CHARACTERISTICS
(V
6
Note 1: V
Note 2: All parameters are 100% tested at T
Note 3: 2-wire serial interface is operational for V
Note 4: See the Detailed Description section (BATT function).
Note 5: I
Note 6: 2-wire serial interface operating at 400kHz, SDA pulled high.
Note 7: For OUT switch over to BATT, V
Note 8: Guaranteed by design. Not production tested.
Note 9: Due to the 2-wire bus timeout feature, there is a minimum specification on the SCL clock frequency based on a 31-byte
Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
Note 11: The maximum t
Note 12: C
Note 13: The maximum t
2-WIRE BUS TIMING
SCL Clock Frequency
Bus Timeout
Bus Free Time Between STOP
and START Condition
Hold Time After (Repeated)
START Condition; After This
Period, the First Clock Is
Generated
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Low to Data Out Valid
SCL Low Period
SCL High Period
SCL/SDA Rise Time
SCL/SDA Fall Time (Receiving)
SCL/SDA Fall Time (Transmitting)
Pulse Width of Spike Suppressed
Capacitive Load of Each Bus
Line
2
CC(MIN)
_______________________________________________________________________________________
C-Compatible Real-Time Clocks with µP
or above V
burst-mode transaction to RAM. See the Timeout Feature section.
in order to bridge the undefined region of the falling edge of SCL.
specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified t
< V
BATT
PARAMETER
RST
B
= total capacitance of one bus line in pF.
CC
is the reset threshold for V
and I
< V
CC(MAX)
BATT
CCS
HD:DAT
F
are specified with SDA and SCLK pulled high, OUT floating, and CE OUT floating.
.
for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t
, T
A
only has to be met if the device does not stretch the LOW period (t
= -40°C to +85°C, unless otherwise noted.) (Note 2)
SYMBOL
t
TIMEOUT
t
t
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:STO
SU:DAT
VD:DAT
t
t
t
f
HIGH
LOW
BUF
SCL
t
C
t
t
t
SP
CC
CC
R
F
F
B
. See the Ordering Information.
must fall below V
A
= +85°C. Limits over temperature are guaranteed by design and not production tested.
(Note 9)
(Notes 10, 11)
(Note 8)
(Note 12)
(Notes 12, 13)
(Notes 12, 13)
(Note 8)
CC
> V
RST
.
RST
F
.
CONDITIONS
and V
BATT
. For OUT switchover to V
20 + 0.1
20 + 0.1
20 + 0.1
0.32
MIN
100
1.3
0.6
0.6
0.6
1.3
0.6
x C
x C
x C
50
1
0
LOW
B
B
B
CC
) of the SCL signal.
, V
TYP
IH min
CC
must be above V
of the SCL signal)
400.00
MAX
300
300
250
400
0.9
50
2
UNITS
kHz
pF
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
s
RST
F
is