1338-31DCGI IDT, 1338-31DCGI Datasheet - Page 14

• Manufacturer Part Number: 1338-31DCGI
• Description: Real Time Clock .9RTC BASE
• Manufacturer: IDT

Specifications of 1338-31DCGI

• Rohs: yes
• Part # Aliases: IDT1338-31DCGI

Timing Diagram
IDT® REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 14
IDT1338
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
Note 7: Measured with a 32.768 kHz crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum t
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement t
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
t
Note 12: C
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter t
voltage range of 0.0V <
SU:DAT
= 1000 + 250 = 1250 ns before the SCL line is released.
B
—total capacitance of one bus line in pF.
V
HD:DAT
OSF
CC
<
is the period of time the oscillator must be stopped for the OSF flag to be set over the
V
CC
need only be met if the device does not stretch the LOW period (t
MAX and 1.3 V < V
BACKUP
< 3.7 V.
IDT1338
SU:DAT
> to 250 ns must
LOW
) of the SCL
REV R 020713
R(MAX)
IHMIN
RTC
+
of