85105AGILF IDT, 85105AGILF Datasheet - Page 12

• Manufacturer Part Number: 85105AGILF
• Description: Clock Drivers & Distribution
• Manufacturer: IDT

Specifications of 85105AGILF

• Product Category: Clock Drivers & Distribution
• Rohs: yes
• Part # Aliases: ICS85105AGILF

ICS85105I Data Sheet
This section provides information on power dissipation and junction temperature for the ICS85105I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85105I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
flow and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
T
ICS85105AGI REVISION A MAY 27, 2011
ABLE
6. T
Multi-Layer PCB, JEDEC Standard Test Boards
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 5 * 47.3mW = 236.5mW
Total Power
The equation for Tj is as follows: Tj =
Tj = Junction Temperature
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
T
85°C + 0.335W * 91.1°C/W = 115.5°C. This is below the limit of 125°C.
JA
A
= Ambient Temperature
HERMAL
= Junction-to-Ambient Thermal Resistance
R
MAX
ESISTANCE
_MAX
= V
MAX
(3.63V, with all outputs switching) = 98.01mW + 236.5mW = 334.51mW
= 47.3mW/Loaded Output pair
DD_MAX
* I
JA
DD_MAX
FOR
= 3.63V * 27mA = 98.01mW
20-L
DD
= 3.3V + 10% = 3.63V, which gives worst case results.
P
EADN
JA
by Velocity (Meters per Second)
OWER
JA
* Pd_total + T
TSSOP, F
C
ORCED
ONSIDERATIONS
A
91.1°C/W
12
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
C
0
ONVECTION
86.7°C/W
1
JA
must be used. Assuming no air
84.6°C/W
2011 Integrated Device Technology, Inc.
2.5