8533AGI-31LF IDT, 8533AGI-31LF Datasheet - Page 11

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8533AGI-31LF

Manufacturer Part Number
8533AGI-31LF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 8533AGI-31LF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS8533AGI-31LF
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50 transmission lines. Matched impedance techniques
8533AGI-01
T
ERMINATION FOR
RTT =
F
((V
IGURE
FOUT
OH
+ V
OL
5A. LVPECL O
) / (V
1
LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
Z
o
50
UTPUT
UTPUTS
T
RTT
ERMINATION
50
V
CC
FIN
- 2V
D
IFFERENTIAL
11
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 5A and 5B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
FOUT
F
-
IGURE
TO
-3.3V LVPECL F
5B. LVPECL O
Z
Z
o
o
= 50
= 50
125
84
UTPUT
ICS8533I-01
L
OW
3.3V
T
125
84
ANOUT
S
ERMINATION
REV. A DECEMBER 6, 2007
KEW
FIN
, 1-
B
UFFER
TO
-4

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