NB100LVEP56MNR2 ON Semiconductor, NB100LVEP56MNR2 Datasheet

IC MUX DUAL 2:1 DIFF ECL 24QFN

NB100LVEP56MNR2

Manufacturer Part Number
NB100LVEP56MNR2
Description
IC MUX DUAL 2:1 DIFF ECL 24QFN
Manufacturer
ON Semiconductor
Series
100LVEPr
Type
Differential Digital Multiplexerr
Datasheet

Specifications of NB100LVEP56MNR2

Circuit
2 x 2:1
Independent Circuits
1
Voltage Supply Source
Dual Supply
Voltage - Supply
2.38 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output High, Low
-
Other names
NB100LVEP56MNOSCT
NB100LVEP56
2.5V / 3.3V ECL DUAL
Differential 2:1 Multiplexer
Description
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both LVECL and LVCMOS input voltage levels. Multiple V
are provided.
this device only. For single−ended input operation, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
Features
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 9
BB
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
The V
V
V
(Compatible with ECL and CMOS Input Voltage Levels)
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
525 ps Typical Propagation Delays
Low Profile QFN Package
PECL Mode Operating Range:
NECL Mode Operating Range:
Separate, Common Select, and Individual Select
Q Output Will Default LOW with Inputs Open or at V
Multiple V
Pb−Free Packages are Available
CC
CC
may also rebias AC coupled inputs. When used, decouple V
CC
= 2.375 V to 3.8 V with V
= 0 V with V
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
pin, an internally generated voltage supply, is available to
BB
Outputs
EE
= −2.375 V to −3.8 V
BB
should be left open.
BB
EE
= 0 V
as a switching reference voltage.
EE
1
BB
pins
BB
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional marking information, refer to
(Note: Microdot may be in either location)
CASE 948E
24 PIN QFN
MN SUFFIX
CASE 485L
DT SUFFIX
TSSOP−20
Application Note AND8002/D.
24
ORDERING INFORMATION
A
L
Y
W
G
1
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
1
DIAGRAMS*
NB100LVEP56/D
MARKING
24
ALYWG
VP56
N100
ALYWG
VP56
N100
G
G

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NB100LVEP56MNR2 Summary of contents

Page 1

NB100LVEP56 2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer Description The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both ...

Page 2

Table 1. PIN FUNCTION DESCRIPTION Pin No. Á Á Á Á Á Á Á Á Á TSSOP QFN Name Á Á Á Á Á Á Á Á Á 14,20 3,9,18,19 15, 3,8 6,12 V ...

Page 3

D0a D0a R 1 D0b D0b R 1 D1a D1a R 1 D1b D1b R 1 Figure 1. Logic Diagram ...

Page 4

Table 4. MAXIMUM RATINGS Symbol Parameter V Positive Mode Power Supply CC V Negative Mode Power Supply EE V Positive Mode Input Voltage I Negative Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 5

Table 6. DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (SEL0, SEL1, COM_SEL) IH Input HIGH Voltage (D Inputs) ...

Page 6

Table 8. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude OUTPP (See Figure Propagation Delay to Output Differential PLH t PHL t Pulse Skew (Note 15) Skew Within Device Input Skew (Note 16) Within Device Output ...

Page 7

PLH Figure 5. AC Reference Measurement Driver Device Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − ...

Page 8

... NB100LVEP56DT NB100LVEP56DTG NB100LVEP56DTR2 NB100LVEP56DTR2G NB100LVEP56MN NB100LVEP56MNG NB100LVEP56MNR2 NB100LVEP56MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *This package is inherently Pb−Free. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D ...

Page 9

... −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE Í Í Í Í ...

Page 10

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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